PCB Stackup Thickness Cheat Sheet

Scope: FR-4 class laminate, Dk approximately 4.2, standard through-hole (non-HDI) construction unless noted. Values are for first-pass stackup selection. Final numbers come from the fabricator's stackup library and field-solver impedance report.

Standard finished thicknesses

Thickness	Imperial	Availability
0.2 / 0.3 mm	-	thin or flex-adjacent, limited layer count, difficult handling
0.4 mm	-	available, depanel with care
0.6 mm	-	available
0.8 mm	0.031"	stocked at all fabricators
1.0 mm	-	stocked at all fabricators
1.2 mm	-	stocked at all fabricators
1.6 mm	0.062"	industry default, stocked at all fabricators
2.0 mm	-	stocked at all fabricators
2.4 mm	0.093"	routine, small cost increase
3.2 mm	0.125"	routine, cost increase, drill limitations

• Default thickness tolerance is ±10%. ±5% is available on request. Controlled dielectric is a separate specification at additional cost.
• 1.6 mm is a historical convention rather than a physical requirement. In the absence of a mechanical constraint, finished thickness is a free design variable.

Thickness budget

Finished thickness is the sum of the copper layers and the dielectric layers:

finished_thickness = Σ(copper) + Σ(dielectric)

copper_total ≈ 2 × t_outer_plated + (N-2) × t_inner
dielectric_count = N - 1

Copper specification	Thickness
0.5 oz inner	0.7 mil (17 µm)
1 oz inner	1.4 mil (35 µm)
2 oz inner	2.8 mil (70 µm)
0.5 oz base + plating (outer)	~1.9 mil
1 oz base + plating (outer)	~2.6 to 2.8 mil

Plating adds approximately 1.2 mil to each outer layer, or 2.4 mil per board, and must be included in the budget.

Average dielectric thickness vs. layer count

Uniform dielectric allocation, 0.5 oz inner layers, plated 0.5 oz outer layers. Values in mils.

Layers	0.8 mm	1.0 mm	1.2 mm	1.6 mm	2.0 mm	2.4 mm
4	8.8	11.4	14.0	-	-	-
6	5.0	6.6	8.1	-	-	-
8	3.4	4.5	5.6	7.9	-	-
10	2.5	3.3	4.2	6.0	-	-
12	-	-	3.3	4.8	6.2	7.6
14	-	-	-	3.9	5.1	-
16	-	-	-	3.3	4.3	5.4
20	-	-	-	2.5	3.3	4.1
24	-	-	-	-	2.6	3.3

Approximate dielectric thickness regimes:

• ≥5 mil: standard prepregs, no special fabrication requirements.
• 3.5 to 5 mil: 1080 and 2116 glass styles. Impedance tolerance is reduced.
• 2.5 to 3.5 mil: specialty materials. Expect tolerance and voltage withstand limitations.
• <2.5 mil: suitable for plane pairs only, not for signal-to-reference spacing.

Impedance constraints

Minimum trace width for a given impedance is determined by dielectric thickness, not by layer count.

Outer layer microstrip, 50 Ω. Trace width is approximately 1.2 to 1.4 × dielectric height.

Dielectric h	Trace w
6 mil	~8 mil
5 mil	~6.5 mil
4 mil	~5.3 mil
3.5 mil	~4.3 mil
3 mil	~3.4 mil

Symmetric stripline, 50 Ω. Plane-to-plane spacing b is approximately 2.8 × trace width.

Trace w	Plane-to-plane b
6 mil	~17 mil
5 mil	~14 mil
4 mil	~11 mil
3.5 mil	~10 mil

Stripline consumes thickness budget approximately 2.5× faster than microstrip because dielectric is required on both sides of the trace.

Layer count at which a uniform 1.6 mm stackup reaches 4/4 mil trace and space:

• stripline: 10 to 12 layers
• microstrip: approximately 14 layers

Below 4/4 mil the design falls outside standard tolerance classes and fabrication cost increases.

Two methods for recovering impedance headroom:

1. Asymmetric dielectric allocation. Reduce power/ground plane pair spacing to 2 to 2.5 mil. Thin plane pairs are desirable for interplane capacitance. Reallocate the recovered thickness to signal-to-reference layers. Typical gain is approximately two layer counts relative to a uniform stackup.
2. Low-Dk laminate. Megtron 6 and equivalent Isola materials at Dk 3.3 to 3.6 achieve 50 Ω with thinner dielectric at the same trace width. Material cost is incurred per panel. The benefit is increased impedance and yield margin.

Copper weight

Inner layer copper weight consumes thickness budget rapidly. Example for a 12 layer board:

Inner copper	Copper thickness at 12L	Feasibility at 1.6 mm
0.5 oz	~11 mil	acceptable
1 oz	~18 mil	marginal
2 oz	~27 mil	not feasible (~3 mil per dielectric)

Heavy copper produces two independent failure modes:

• Budget. Thickness is consumed by copper rather than dielectric.
• Resin fill. Thin prepreg cannot supply sufficient resin to fill etched gaps around 2 oz features. Prepreg resin content must be matched to the copper it fills. Mismatch results in voids and delamination.

Designs requiring heavy power planes should be specified at 2.0 to 2.4 mm.

Voltage and dielectric spacing

IPC-2221 Table 6-1 specifies conductor-to-conductor spacing (in-plane creepage). Applying column B1 (internal) to layer-to-layer dielectric thickness is conservative, but it is accepted industry practice and is the criterion a safety reviewer will apply.

B1 internal values, recalled from memory. Verify against the current document. Table values changed between 2221B and 2221C.

Working voltage	Min spacing	In mils
0 to 30 V	0.05 mm	2.0
31 to 100 V	0.10 mm	3.9
101 to 300 V	0.20 mm	7.9
301 to 500 V	0.25 mm	9.8
>500 V	0.0025 mm/V	-

By this table, 3 mil (0.076 mm) is limited to 30 V. 3.94 mil is required to claim 100 V.

Material breakdown strength is approximately two orders of magnitude higher. Cured FR-4 breaks down at roughly 800 to 1500 V/mil, so 3 mil withstands 2 to 4 kV. The derating in the table accounts for voids, resin starvation, glass weave, and lamination defects rather than the bulk resin. In practice 3 mil at 48 V performs reliably, but it does not satisfy the table requirement and cannot be justified by it in a safety review.

Reinforced insulation through solid material (IEC 60664-1 / IEC 62368-1) requires one of the following:

• ≥0.4 mm of solid material, or
• ≥2 layers, each passing the reinforced test voltage, or
• ≥3 layers, where any two pass

A single 3 mil prepreg never qualifies as reinforced insulation, regardless of hipot results. Basic insulation has no thickness minimum and is qualified by withstand test only.

IPC-9592B (power conversion) is more granular. It accounts for pollution degree, altitude, and functional/basic/reinforced classification, and treats laminated internal layers as solid insulation rather than a creepage path. Consult the document directly.

Conductive anodic filament (CAF) growth is the dominant long-term failure mode in thin, high layer count boards. It is a hole-to-hole and hole-to-plane spacing problem along glass bundles, and is not addressed by the IPC-2221 spacing tables. Specify CAF-resistant laminate and maintain drill-to-drill spacing ≥15 mil in high-field regions.

Drill aspect ratio

Standard through-hole plating supports an aspect ratio of 8:1 to 10:1. Minimum drill diameter is finished thickness divided by aspect ratio.

Thickness	Min drill @10:1	Min drill @8:1
0.8 mm	0.08 mm*	0.10 mm*
1.0 mm	0.10 mm*	0.13 mm
1.6 mm	0.16 mm	0.20 mm
2.0 mm	0.20 mm	0.25 mm
2.4 mm	0.24 mm	0.30 mm
3.2 mm	0.32 mm	0.40 mm

* limited by the minimum mechanical drill, approximately 0.15 mm at most fabricators

Thickness constrains via geometry independently of layer count. At 3.2 mm, via-in-pad on fine pitch BGA packages is generally impractical.

Additional constraints

Issue	Effect	Mitigation
Registration	layer-to-layer misregistration accumulates with layer count	relax annular ring at 12L and above, or move to HDI
Warp	asymmetric copper bows the panel during lamination and again at reflow	balance copper weight and coverage per layer, add thieving; worse on thin boards with large BGAs
Cost	layer count is the dominant cost driver	12L is approximately 1.5 to 2× the cost of 8L
Yield	thin dielectric and fine lines compound	expect scrap above 16L at <3.5 mil
Connector fit	edge connectors, press-fit, and card slots assume 1.6 mm	verify that the constraint applies to the design before designing to it

Decision procedure

1. Mechanical constraint. Card edge, press-fit, enclosure slot, or panel rails fix the thickness. Otherwise thickness is a free variable.
2. Copper weight from current requirements. Inner layers ≥2 oz require 2.0 mm minimum, typically 2.4 mm.
3. Isolation requirement. Reinforced insulation requires ≥0.4 mm through the barrier or a multi-ply construction. Thin stackups do not meet this requirement.
4. Layer count from routing density.
5. Asymmetric dielectric allocation. Plane pairs thin, signal-to-reference thick.
6. Impedance feasibility at the resulting dielectric thicknesses. Below 4/4 mil: add thickness, reduce layer count, or change to low-Dk material.
7. Drill aspect ratio against the smallest via.
8. HDI evaluation. When layer count is driven by BGA escape routing, a 1+N+1 construction with laser microvias at 8 to 10 layers typically has lower cost and better signal integrity than 14 through-hole layers.

Limitations of these values

• Impedance figures are IPC-2141 closed-form approximations. They deviate 5 to 10% from a 2D field solver and do not model etch taper, glass weave Dk variation, or solder mask. Solder mask alone reduces outer layer impedance by 2 to 3 Ω.
• Use these tables for first-pass stackup selection, then obtain the fabricator's field-solver impedance report before release.
• Fabricator capability tables change frequently. Obtain the current stackup library from the quoting fabricator, particularly above 12 layers.
• IPC table values are recalled, not read from the standard. Verify before release or submission.