PCB Stackup Thickness Cheat Sheet

Scope: FR-4 class laminate, relative dielectric constant Dk approximately 4.2, standard through-hole construction (no HDI, high density interconnect, microvia layers) unless noted. Values are for first-pass stackup selection. Final numbers come from the fabricator's stackup library and field-solver impedance report.

Standard finished thicknesses

How much a standard finished thickness matters depends on layer count. A 2-layer board is a single copper-clad core, so its finished thickness is a laminate the fabricator has to stock. A multilayer board is built from cores and prepreg, so its finished thickness is a construction choice, and nearly any value is available from stock material.

2-layer boards (single core).

Anything not in the table is a special-order laminate for a 2-layer board.

Multilayer boards. Fabricators do not stock finished thicknesses. They stock:

• cores, roughly 2.5 to 59 mil, in a handful of copper weights
• a handful of prepreg glass styles (106, 1080, 2113, 2116, 3313, 7628) in one or two resin contents each

The stackup combines these to hit the target, so any finished thickness within ±10% can be built from stock material. The real constraints on multilayer finished thickness are mechanical: mating hardware (edge connectors, PCIe expects 1.57 mm; card guides; press-fit pin length ranges; wave solder pallets) and plated-hole aspect ratio (see Drill aspect ratio).

The exception is the budget fabricator (JLCPCB, PCBWay, and similar). There "standard stackup" is literal: a fixed menu of published stackups at each thickness and layer count. Going off the menu leaves the low-cost service and reprices the board as a custom build.

• Default thickness tolerance is ±10%. ±5% is available on request. Controlled dielectric is a separate specification at additional cost.
• 1.6 mm is a historical convention rather than a physical requirement. In the absence of a mechanical constraint, finished thickness is a free design variable.
• Core and prepreg inventories vary by fabricator and change over time. The fabricator's published material list is the authoritative source.

Thickness budget

Finished thickness is the sum of the copper layers and the dielectric layers:

finished_thickness = Σ(copper) + Σ(dielectric)

copper_total ≈ 2 × t_outer_plated + (N-2) × t_inner
dielectric_count = N - 1

N is the layer count, t_inner the inner layer foil thickness, and t_outer_plated the outer layer copper thickness after plating. The shorthand nL means an n-layer board (12L is 12 layers).

Plating adds approximately 1.2 mil to each outer layer, or 2.4 mil per board, and must be included in the budget.

Average dielectric thickness vs. layer count

Uniform dielectric allocation, 0.5 oz inner layers, plated 0.5 oz outer layers. Values in mils.

Approximate dielectric thickness regimes:

• ≥5 mil: standard prepregs, no special fabrication requirements.
• 3.5 to 5 mil: 1080 and 2116 glass styles. Impedance tolerance is reduced.
• 2.5 to 3.5 mil: specialty materials. Expect tolerance and voltage withstand limitations.
• <2.5 mil: suitable for plane pairs only, not for signal-to-reference spacing.

Impedance constraints

Minimum trace width for a given impedance is determined by dielectric thickness, not by layer count.

Symbols: w is trace width. h is the dielectric thickness between a microstrip trace and its reference plane. b is the total dielectric thickness between the two reference planes of a stripline, measured plane to plane; a symmetric stripline trace sits at b/2 with equal dielectric above and below. All are in mils unless stated.

Outer layer microstrip, 50 Ω. Trace width is approximately 1.2 to 1.4 × dielectric height.

Symmetric stripline, 50 Ω. Plane-to-plane spacing b is approximately 2.8 × trace width.

Stripline consumes thickness budget approximately 2.5× faster than microstrip because dielectric is required on both sides of the trace.

Layer count at which a uniform 1.6 mm stackup reaches 4/4 mil trace and space (4 mil trace width, 4 mil gap):

• stripline: 10 to 12 layers
• microstrip: approximately 14 layers

Below 4/4 mil the design falls outside standard tolerance classes and fabrication cost increases.

Two methods for recovering impedance headroom:

1. Asymmetric dielectric allocation. Reduce power/ground plane pair spacing to 2 to 2.5 mil. Thin plane pairs are desirable for interplane capacitance. Reallocate the recovered thickness to signal-to-reference layers. Typical gain is approximately two layer counts relative to a uniform stackup.
2. Low-Dk laminate. Megtron 6 and equivalent Isola materials at Dk 3.3 to 3.6 achieve 50 Ω with thinner dielectric at the same trace width. Material cost is incurred per panel. The benefit is increased impedance and yield margin.

Copper weight

Inner layer copper weight consumes thickness budget rapidly. Example for a 12 layer board:

Heavy copper produces two independent failure modes:

• Budget. Thickness is consumed by copper rather than dielectric.
• Resin fill. Thin prepreg cannot supply sufficient resin to fill etched gaps around 2 oz features. Prepreg resin content must be matched to the copper it fills. Mismatch results in voids and delamination.

Designs requiring heavy power planes should be specified at 2.0 to 2.4 mm.

Voltage and dielectric spacing

IPC-2221 Table 6-1 specifies conductor-to-conductor spacing (in-plane creepage). Applying column B1 (internal) to layer-to-layer dielectric thickness is conservative, but it is accepted industry practice and is the criterion a safety reviewer will apply.

B1 internal values, recalled from memory. Verify against the current document. Table values changed between 2221B and 2221C.

By this table, 3 mil (0.076 mm) is limited to 30 V. 3.94 mil is required to claim 100 V.

Material breakdown strength is approximately two orders of magnitude higher. Cured FR-4 breaks down at roughly 800 to 1500 V/mil, so 3 mil withstands 2 to 4 kV. The derating in the table accounts for voids, resin starvation, glass weave, and lamination defects rather than the bulk resin. In practice 3 mil at 48 V performs reliably, but it does not satisfy the table requirement and cannot be justified by it in a safety review.

Reinforced insulation through solid material (IEC 60664-1 / IEC 62368-1) requires one of the following:

• ≥0.4 mm of solid material, or
• ≥2 layers, each passing the reinforced test voltage, or
• ≥3 layers, where any two pass

A single 3 mil prepreg never qualifies as reinforced insulation, regardless of hipot results. Basic insulation has no thickness minimum and is qualified by withstand test only.

IPC-9592B (power conversion) is more granular. It accounts for pollution degree, altitude, and functional/basic/reinforced classification, and treats laminated internal layers as solid insulation rather than a creepage path. Consult the document directly.

Conductive anodic filament (CAF) growth is the dominant long-term failure mode in thin, high layer count boards. It is a hole-to-hole and hole-to-plane spacing problem along glass bundles, and is not addressed by the IPC-2221 spacing tables. Specify CAF-resistant laminate and maintain drill-to-drill spacing ≥15 mil in high-field regions.

Drill aspect ratio

Standard through-hole plating supports an aspect ratio of 8:1 to 10:1. Minimum drill diameter is finished thickness divided by aspect ratio.

* limited by the minimum mechanical drill, approximately 0.15 mm at most fabricators

Thickness constrains via geometry independently of layer count. At 3.2 mm, via-in-pad on fine pitch BGA packages is generally impractical.

Additional constraints

Material portability between fabricators

The goal of the stackup specification is a board that any competent fabricator can build from stock material, so that a second source is a requote rather than a redesign. The PCB atlas maps fabricators and assembly houses by region, capability, certification, and cost tier for second-source selection. Availability problems come from the specification, not from the thickness:

• Over-specified construction. Naming an exact laminate brand, glass style, core thickness, and resin content forces the fabricator to buy material it may not stock, and a second fabricator to buy material it never stocks.
• Specialty laminates. RO4350B and RO4003C are stocked at most RF-capable shops. Megtron 6 and 7, spread-glass styles, and embedded-capacitance cores can mean weeks of lead time and minimum material buys.
• Heavy copper, 3 oz and up on inner layers. High-resin prepreg is required to fill between traces, which narrows the viable constructions and the list of shops.
• High-voltage isolation. Safety standards such as IEC 62368-1 can dictate prepreg ply count between layers, not only dielectric thickness. Verify against the current clause before writing the note.
• Vendor-locked Dk. A stackup tuned to one vendor's Dk to two decimals does not port. Controlled impedance drifts when the material changes, so the second fabricator must re-solve the widths, which the fab note should permit.

Regional material families. Chinese and Taiwanese fabricators run Shengyi, Kingboard, Nan Ya, ITEQ, and EMC laminate. US and European fabricators run Isola, Ventec, Panasonic, and Rogers. The families overlap by class, and a stackup specified by class ports between them. Equivalence is by IPC-4101 slash sheet and datasheet Tg, Td, Dk, and Df, not by brand.

Product names and slash sheet numbers are recalled, not read from the standard or datasheets. Verify the current IPC-4101 revision and the fabricator's material list before release.

Fab note wording. Specify the result and the limits, name the material by class with "or equivalent", and let the fabricator choose the construction:

1. Material: FR-4 per IPC-4101/126 or /129, Tg 170 °C min, Td 340 °C min,
   or equivalent. Fabricator to propose the stackup; approval required
   before fabrication.
2. Layer count 8. Finished thickness 1.60 mm ±10% over solder mask.
3. Copper: outer layers 0.5 oz base, plated to 1 oz minimum finished.
   Inner layers 0.5 oz; L4 and L5 1 oz.
4. Controlled impedance: 50 Ω ±10% single-ended on L1, L3, L6, L8 and
   100 Ω ±10% differential on L3 and L6 at the widths shown. Fabricator
   may adjust trace width and spacing up to ±20% to meet impedance.
   Report the final stackup and widths with the quote.
5. Minimum dielectric 4 mil between any two copper layers. Minimum two
   plies of prepreg between L2 and L3 (isolation barrier).

Avoid in the note:

• a laminate brand or product name without "or equivalent" (except RF laminates where the brand is the specification)
• prepreg glass style and resin content
• core thickness to a fraction of a mil
• Dk to two decimals
• a thickness tolerance tighter than ±10% without a reason that survives a cost review

Request the fabricator's proposed stackup before routing controlled-impedance nets, and send the same request to the second source at the same time. Two proposed stackups that agree on dielectric thickness within a mil mean the design ports; a disagreement is cheaper to resolve before routing than after.

Decision procedure

1. Mechanical constraint. Card edge, press-fit, enclosure slot, or panel rails fix the thickness. Otherwise thickness is a free variable.
2. Copper weight from current requirements. Inner layers ≥2 oz require 2.0 mm minimum, typically 2.4 mm.
3. Isolation requirement. Reinforced insulation requires ≥0.4 mm through the barrier or a multi-ply construction. Thin stackups do not meet this requirement.
4. Layer count from routing density.
5. Asymmetric dielectric allocation. Plane pairs thin, signal-to-reference thick.
6. Impedance feasibility at the resulting dielectric thicknesses. Below 4/4 mil: add thickness, reduce layer count, or change to low-Dk material.
7. Drill aspect ratio against the smallest via.
8. HDI evaluation. When layer count is driven by BGA escape routing, a 1+N+1 construction (one laser microvia layer on each side of an N-layer through-hole core) at 8 to 10 layers typically has lower cost and better signal integrity than 14 through-hole layers.
9. Portability check. Material called out by IPC-4101 class with "or equivalent", no glass style or resin content in the note, impedance widths left adjustable, and a proposed stackup in hand from the primary and the second source before controlled-impedance routing.

Limitations of these values

• Impedance figures are IPC-2141 closed-form approximations. They deviate 5 to 10% from a 2D field solver and do not model etch taper, glass weave Dk variation, or solder mask. Solder mask alone reduces outer layer impedance by 2 to 3 Ω.
• Use these tables for first-pass stackup selection, then obtain the fabricator's field-solver impedance report before release.
• Fabricator capability tables change frequently. Obtain the current stackup library from the quoting fabricator, particularly above 12 layers.
• IPC table values are recalled, not read from the standard. Verify before release or submission.