Op-Amp Circuit Cheat Sheet

Scope: voltage-feedback operational amplifiers in closed-loop linear circuits, plus the comparator cases where op-amps are commonly misapplied. Component values in the figures are worked examples, not recommendations. Part numbers in the selection tables are representative and should be verified against current datasheets.

Ideal model and where it fails

The ideal op-amp analysis rests on two rules: no current flows into either input, and with negative feedback the output does whatever is required to make the two inputs equal. Every design error in this document is a case where one of the assumptions behind those rules stops holding.

Datasheet parameters

Resistor thermal noise for reference: $\sqrt{4kTR} = 4.07\ \text{nV}/\sqrt{\text{Hz}}$ for 1 kΩ at 300 K, scaling with $\sqrt{R}$. 100 Ω gives 1.3 nV/√Hz. 10 kΩ gives 12.9 nV/√Hz.

Common design errors

Each entry states the mechanism and the correction.

Input side

1. Common-mode range violated in a non-inverting stage. The non-inverting input follows the signal, so the full signal must lie inside the input common-mode range. A single-supply amplifier whose inputs do not include ground cannot buffer a signal that goes to 0 V. Correction: choose a part whose input range includes the required rail, or use an inverting configuration, where the common-mode voltage is fixed at the non-inverting input's bias point regardless of signal amplitude.
2. Phase reversal. On some bipolar and JFET input stages (LM324, LF353, TL07x, and other older designs), driving an input beyond the common-mode range inverts the output rather than clipping it. In a feedback loop this becomes positive feedback and the stage latches. Correction: series input resistance with clamp diodes, or a part that specifies no phase reversal.
3. Bias current times source resistance. A 100 nA bipolar bias current into a 100 kΩ source produces 10 mV of offset, multiplied by the noise gain. Correction: match the DC resistance seen by both inputs (the $R_b = R_1 \| R_f$ resistor in the inverting amplifier figure) so that only $I_{OS}$ remains, or use a JFET or CMOS input part. The matching resistor adds thermal noise and is omitted in low-noise designs.
4. Bias current doubling with temperature. JFET and CMOS bias current is leakage and doubles roughly every 10 °C. A 1 pA specification at 25 °C becomes 128 pA at 95 °C. Correction: read the bias current vs. temperature plot, not the 25 °C table value.
5. Current noise into high source impedance. With a 1 MΩ source, a bipolar amplifier with 1 pA/√Hz current noise contributes 1 µV/√Hz, far above its 1 nV/√Hz voltage noise. Correction: above roughly 10 to 50 kΩ source resistance, JFET or CMOS inputs give lower total noise despite higher voltage noise. The crossover is at $R_s = e_n / i_n$.
6. Input differential clamps. Precision and low-noise bipolar parts often have anti-parallel diodes across the inputs. Any circuit that opens the loop (comparator use, power-up transients, input overdrive, large-signal slewing in an integrator reset) forces current through them. Correction: series input resistance sized to limit current to the datasheet value, typically 1 to 10 mA.
7. Rail-to-rail input crossover. Rail-to-rail input stages usually consist of two differential pairs, one PNP or PMOS pair for low common-mode voltages and one NPN or NMOS pair for high. The handover, typically 1 to 1.5 V below the positive rail, produces a step in offset voltage and in bias current, which appears as distortion when the signal crosses that region. Correction: keep the common-mode voltage on one side of the crossover, use an inverting configuration, or use a zero-crossover part (charge-pump biased single pair, for example OPA365, OPA2189, TLV9xx families with that feature).
8. Floating unused amplifiers. An unused section of a dual or quad with open inputs drifts to a rail and can oscillate or raise supply current. Correction: connect it as a unity-gain follower with the non-inverting input tied to a voltage inside the common-mode range, typically mid-supply or ground on a dual supply.
9. Input beyond the supply at power-up or with the supply off. Signal present before the supply rises flows through the ESD structure into the supply rail. CMOS parts can latch up. Correction: series resistance, external clamp diodes to the rails, or an amplifier with over-voltage tolerant inputs.
10. Leakage at femtoamp and picoamp levels. Board leakage across 10 GΩ from a 5 V trace is 500 pA, which exceeds the bias current of an electrometer amplifier by orders of magnitude. Correction: guard ring driven at the input potential around the sensitive node, no solder mask over the guard, clean the board, and consider air-wired or PTFE-standoff input nodes.

Feedback network and stability

11. Feedback resistor too large. The op-amp input capacitance (typically 2 to 10 pF, plus board capacitance) forms a pole with $R_f \| R_g$ in the feedback path. With $R_f = 1\ \text{M}\Omega$ and 5 pF, the pole is at 32 kHz, well inside the loop bandwidth of most amplifiers, and the stage rings or oscillates. Correction: a feedback capacitor $C_f$ across $R_f$ with $R_f C_f \geq R_g C_{in}$, or lower resistor values.
12. Feedback resistor too small. The output drives $R_f + R_g$ to ground in parallel with the load. 100 Ω values at 10 V demand 100 mA and exceed the output current rating. Correction: keep the feedback network in the 1 kΩ to 100 kΩ range for general-purpose parts, lower only for high-speed parts that specify it.
13. Capacitive load. The open-loop output impedance and the load capacitance form a pole inside the loop. 100 pF of coaxial cable is enough to destabilize many amplifiers. Correction: series isolation resistor of 10 to 100 Ω outside the loop, or the in-loop compensation arrangement in the capacitive load figure below. Datasheet overshoot vs. capacitive load plots give the limit.
14. Decompensated amplifiers at low gain. Parts specified for a minimum gain of 5 or 10 have less internal compensation and more bandwidth, and oscillate at unity gain. Correction: check the minimum stable gain. If unity gain is needed, use a fully compensated part or add a noise-gain compensation network.
15. Noise gain vs. signal gain. Bandwidth, offset multiplication, and stability all depend on noise gain $1 + R_f/R_g$, not on signal gain. An inverting amplifier with gain of -1 has a noise gain of 2 and half the bandwidth of a unity-gain follower. Correction: design and check stability against noise gain.
16. Sallen-Key high-frequency feedthrough. Above the passband, the Sallen-Key filter relies on the op-amp output being a low impedance. The op-amp's output impedance rises with frequency as loop gain falls, and signal feeds through the feedback capacitor directly to the output. Attenuation stops improving and can return toward 0 dB. Correction: multiple feedback (MFB) topology for stopband attenuation above about 40 dB or for high Q, or a passive RC stage after the Sallen-Key.
17. Filter Q sensitivity. Sallen-Key filters with gain greater than 1 have Q that depends on the gain-setting resistor ratio, and Q above about 3 becomes impractical with standard tolerance parts. Correction: unity-gain Sallen-Key or MFB for high Q, 1% or better components, and a check of the sensitivity of Q to each element.
18. Integrator drift. An integrator with no DC path around the capacitor integrates $V_{OS}$ and $I_B$ until the output saturates. Correction: a large resistor $R_f$ across $C_f$ that sets the DC gain to $R_f/R_1$, or a periodic reset switch.
19. Differentiator noise and instability. A pure differentiator has gain rising at 20 dB/decade without limit and a feedback network that is purely capacitive at high frequency, which produces a 90° phase lag inside the loop. Correction: series input resistor $R_s$ and feedback capacitor $C_f$ that flatten the gain above the frequency of interest.
20. Difference amplifier CMRR limited by resistor matching. The four-resistor difference amplifier rejects common-mode signals only as well as the resistor ratios match. With 1% resistors, worst-case CMRR at unity gain is about 34 dB; with 0.1%, about 54 dB. The op-amp's own CMRR is usually irrelevant. Correction: matched resistor networks (0.01% ratio match), or an instrumentation amplifier where the resistors are trimmed on the die.
21. Difference amplifier input impedance. The two inputs see different and signal-dependent impedances ($R_1$ on the inverting side, $R_3 + R_4$ on the other), so source resistance unbalances the ratios and degrades CMRR. Correction: buffer the inputs, or use an instrumentation amplifier.

Output side

22. Output swing on non-rail-to-rail parts. A bipolar output stage typically stops 1 to 2 V from each rail. On a 5 V single supply, the usable output can be 1 to 3.5 V. Correction: rail-to-rail output part, higher supply, or check the output swing vs. load current plot at the actual load.
23. Rail-to-rail output is not zero ohms to the rail. A rail-to-rail output stage is a common-source or common-emitter transistor, so the saturation voltage scales with load current. At 10 mA, 100 to 300 mV from the rail is typical. Correction: read the swing specification at the load current in use.
24. Class-B crossover distortion. The LM358 and LM324 output stage has no idle current through the crossover region, which produces a dead zone as the output passes through zero load current. Correction: a pull-down resistor from the output to the negative rail that keeps the output sourcing current, or a part with a class-AB output.
25. Driving ADC inputs. A SAR ADC's sampling capacitor draws a charge spike at the start of each acquisition. Driving it directly from the amplifier produces settling errors and can cause the amplifier to ring. Correction: RC filter between the amplifier and the ADC, sized per the ADC driver figure below.
26. Op-amp as comparator. Open-loop use saturates the output stage, and recovery from saturation takes microseconds. Input clamps conduct. Output swing may not reach logic levels. There is no hysteresis, so noise near the threshold produces multiple transitions. Correction: a comparator, which has an open-loop output stage designed for saturation, defined logic levels, and specified propagation delay. Add hysteresis with positive feedback.

Supply, layout, and single-supply operation

27. Decoupling. Missing or distant decoupling raises supply impedance at the frequencies where PSRR is already poor, and the amplifier oscillates through the supply. Correction: 100 nF ceramic within a few millimeters of each supply pin, with a return path to the ground reference of the feedback network, plus bulk capacitance per group.
28. Virtual ground on a single supply. A resistive divider alone has an impedance of $R/2$ and is modulated by any current the circuit returns to it. Correction: buffer the mid-rail with an op-amp (rail splitter figure) or a dedicated part such as the TLE2426, and decouple the divider node.
29. AC coupling corner frequencies. Each coupling capacitor with its bias resistor forms a high-pass corner at $1/(2\pi RC)$, and in the single-supply non-inverting amplifier the gain resistor's capacitor forms a second corner. Cascaded corners at the same frequency produce -6 dB at that frequency, not -3 dB. Correction: place the corners at least a decade below the lowest signal frequency, and account for start-up settling of large capacitors.
30. Ground return of the feedback network. The gain-setting resistor's ground defines the output reference. If it returns to a point carrying load current, the load current's IR drop appears in series with the input signal, multiplied by the gain. Correction: star the feedback ground, the input signal ground, and the decoupling ground at a single point.
31. Thermocouple junctions. Dissimilar metal junctions at solder joints, connectors, and relay contacts generate microvolts per degree. In a circuit with 1 µV offset, one junction with a 1 °C gradient across it dominates. Correction: symmetrical layout so junctions cancel, avoid airflow across the input stage, low-thermal-EMF relays.
32. Chopper and auto-zero artifacts. Zero-drift amplifiers switch their input stage at 10 kHz to several MHz. Charge injection produces current spikes at the inputs, which become voltage noise into high source impedance, and the chopping frequency and its intermodulation products appear in the output spectrum. Correction: keep source impedance low, filter the output below the chopping frequency, and avoid these parts for wideband signals near the switching frequency.
33. Resistor tolerance and temperature coefficient in gain accuracy. 1% resistors give 2% worst-case gain error; 100 ppm/°C resistors drift 1000 ppm over 100 °C. Correction: 0.1% and 25 ppm/°C for precision gain, or matched networks in one package where tracking rather than absolute tolerance matters.

Standard circuits

Design equations use the reference designators in each figure.

Voltage follower

Figure 1. Voltage follower.

$V_{out} = V_{in}$. Noise gain 1, so full GBW and full offset accuracy. The input must lie inside the common-mode range and the output inside the swing range for the entire signal. This is the configuration most sensitive to capacitive load and to unity-gain stability. Use: impedance transformation, driving ADC inputs through an RC, isolating a filter stage from its load.

Non-inverting amplifier

Figure 2. Non-inverting amplifier.

$$V_{out} = \left(1 + \frac{R_f}{R_g}\right) V_{in}$$

Noise gain equals signal gain. Input impedance is that of the op-amp input itself. Common-mode voltage equals the input signal, so the input range requirement is the same as for the follower. Bandwidth $= GBW / (1 + R_f/R_g)$. Gain cannot be less than 1. The figure gives gain 10 and, for a 10 MHz GBW part, 1 MHz bandwidth.

Inverting amplifier

Figure 3. Inverting amplifier with bias-current compensation.

$$V_{out} = -\frac{R_f}{R_1} V_{in}$$

Input impedance is $R_1$. The inverting input sits at the potential of the non-inverting input (a virtual ground here), so the common-mode voltage is constant regardless of signal amplitude. This makes the inverting configuration the correct choice when the signal exceeds the input common-mode range or when the input stage has a crossover region. Noise gain is $1 + R_f/R_1$, so a gain of -10 has the same bandwidth as a non-inverting gain of 11. $R_b = R_1 \| R_f$ cancels the bias-current offset on bipolar input parts and is omitted on JFET and CMOS parts and in low-noise designs. Gain can be less than 1.

Inverting amplifier with bandwidth limit

Figure 4. Inverting amplifier with first-order roll-off.

$$\frac{V_{out}}{V_{in}} = -\frac{R_f}{R_1} \cdot \frac{1}{1 + s R_f C_f}, \qquad f_c = \frac{1}{2\pi R_f C_f}$$

The feedback capacitor rolls the gain off at 20 dB/decade above $f_c$ and also compensates the input-capacitance pole from error 11. The figure gives gain -10 with $f_c$ = 10 kHz. This is the standard single-ended gain-plus-filter stage for anti-aliasing before an ADC, sensor conditioning, and noise bandwidth limiting. The roll-off is first order. For steeper roll-off, follow it with a Sallen-Key or MFB stage.

Single-supply AC-coupled non-inverting amplifier

Figure 5. Single-supply AC-coupled non-inverting amplifier.

$$A_{V,AC} = 1 + \frac{R_f}{R_g}, \qquad A_{V,DC} = 1$$

$R_{b1}$ and $R_{b2}$ bias the non-inverting input at $V_{CC}/2$. $C_g$ makes the DC gain unity so that the bias point, offset, and bias-current error are not multiplied by the AC gain. Three high-pass corners exist: $C_{in}$ with $R_{b1} \| R_{b2}$, $C_g$ with $R_g$, and any output coupling capacitor with its load. In the figure: 3.2 Hz at the input, 15.9 Hz at $R_g C_g$. The bias divider's impedance ($R_{b1} \| R_{b2}$ = 50 kΩ) sets the input impedance and converts bias current to offset. Output swing is centered at $V_{CC}/2$ and limited to the output swing specification on each side.

Summing amplifier

Figure 6. Inverting summing amplifier.

$$V_{out} = -R_f \left( \frac{V_1}{R_1} + \frac{V_2}{R_2} + \frac{V_3}{R_3} \right)$$

Each input is isolated from the others by the virtual ground, so the sources do not interact. Noise gain is $1 + R_f / (R_1 \| R_2 \| R_3)$, which grows with the number of inputs and reduces bandwidth and increases offset accordingly. Use: audio mixing, adding a DC offset to a signal, digital-to-analog conversion with binary-weighted resistors.

Difference amplifier, unity gain

Figure 7. Unity-gain difference amplifier.

$$V_{out} = \frac{R_2}{R_1}(V_2 - V_1) \quad \text{when} \quad \frac{R_2}{R_1} = \frac{R_4}{R_3}$$

With all four resistors equal, $V_{out} = V_2 - V_1$. CMRR is set by resistor ratio matching (error 20), and the two inputs present different impedances (error 21). The common-mode voltage at the op-amp inputs is $V_2 \times R_4/(R_3+R_4)$, which is half of $V_2$ at unity gain. This is how a difference amplifier accepts common-mode voltages beyond the op-amp's supply: the divider attenuates them. Dedicated difference amplifiers (INA105, AD8276, INA149) integrate the matched network and specify CMRR directly. Use: ground-loop breaking, current shunt measurement with the shunt at a moderate common-mode voltage, converting a differential signal to single-ended.

Difference amplifier with gain and filtering

Figure 8. Difference amplifier with gain of 10 and first-order low-pass.

$$V_{out} = \frac{R_2}{R_1}(V_2 - V_1) \cdot \frac{1}{1 + s R_2 C_2}, \qquad R_2 C_2 = R_4 C_4$$

The capacitor pair must match as closely as the resistor pair, because an imbalance in the two time constants degrades CMRR at frequencies near the corner and above. With 5% capacitors the AC CMRR is limited to about 26 dB near $f_c$. For gain and filtering with high CMRR, use an instrumentation amplifier followed by a single-ended filter, or a matched-network difference amplifier followed by the filter. The figure gives gain 10 with $f_c$ = 15.9 kHz.

Instrumentation amplifier

Figure 9. Three op-amp instrumentation amplifier.

$$V_{out} = \left(1 + \frac{2 R_1}{R_G}\right) \frac{R_4}{R_3} (V_1 - V_2) + V_{REF}$$

The input buffers A1 and A2 present the full op-amp input impedance on both inputs and take the differential gain, while common-mode signals pass through them at unity gain. The difference stage A3 then removes the common-mode component, and its resistor matching requirement is relaxed by the differential gain already taken. Gain is set by a single resistor $R_G$. Integrated parts trim $R_1$ through $R_4$ on die and specify CMRR of 80 to 120 dB.

Constraints specific to instrumentation amplifiers:

• The internal node voltages, not just the inputs, must stay inside the buffer amplifiers' swing. The allowable combination of common-mode voltage and output voltage is given in the datasheet as a diamond-shaped plot. At high gain and high common-mode voltage the usable range collapses.
• The REF pin must be driven from a low impedance. Resistance in series with REF unbalances $R_4$ and degrades CMRR. Use a buffer if REF is derived from a divider.
• Both inputs need a DC return path for bias current. A floating source (transformer, capacitively coupled electrodes) requires bias resistors to ground or to the REF potential.
• Gain accuracy depends on the external $R_G$ tolerance and temperature coefficient as well as the internal trim.

Sallen-Key low-pass

Figure 10. Second-order Sallen-Key low-pass, unity gain, Butterworth.

$$f_0 = \frac{1}{2\pi \sqrt{R_1 R_2 C_1 C_2}}, \qquad Q = \frac{\sqrt{R_1 R_2 C_1 C_2}}{C_2 (R_1 + R_2)}$$

With $R_1 = R_2 = R$: $Q = \frac{1}{2}\sqrt{C_1 / C_2}$. Butterworth ($Q = 0.707$) requires $C_1 = 2 C_2$. Bessel ($Q = 0.577$) requires $C_1 = 1.33 C_2$. The figure gives $f_0$ = 1.13 kHz Butterworth. Non-inverting, so the input impedance is high and the passband gain is exactly 1 with no resistor dependence. Limitations: high-frequency feedthrough (error 16) and Q sensitivity (error 17). Cascade two stages with the Q values from a filter table for fourth order. The op-amp must have GBW at least 100 times $f_0 \times Q$ for the response to match the design values.

Sallen-Key high-pass

Figure 11. Second-order Sallen-Key high-pass, unity gain, Butterworth.

$$f_0 = \frac{1}{2\pi \sqrt{R_1 R_2 C_1 C_2}}, \qquad Q = \frac{1}{2}\sqrt{\frac{R_2}{R_1}} \quad (C_1 = C_2)$$

Butterworth requires $R_2 = 2 R_1$. The figure gives $f_0$ = 1.13 kHz. The input capacitors block DC, so the non-inverting input's bias current flows through $R_2$ and produces an offset of $I_B \times R_2$. Use JFET or CMOS input parts for large $R_2$. The high-frequency limit of the passband is set by the op-amp's GBW, above which the response falls off again.

Multiple-feedback low-pass

Figure 12. Second-order multiple-feedback low-pass, gain -1, Butterworth.

$$\frac{V_{out}}{V_{in}} = -\frac{R_3 / R_1}{1 + s C_2 \left(R_2 + \dfrac{R_2 R_3}{R_1}\right) + s^2 R_2 R_3 C_1 C_2}$$ $$f_0 = \frac{1}{2\pi \sqrt{R_2 R_3 C_1 C_2}}, \qquad Q = \frac{\sqrt{R_2 R_3 C_1 C_2}}{C_2 R_2 (1 + R_3 / R_1)}$$

With $R_1 = R_2 = R_3$: $Q = \frac{1}{2}\sqrt{C_1 / C_2}$, and Butterworth again requires $C_1 = 2 C_2$. Inverting, and the passband gain $-R_3/R_1$ is set independently of Q. The inverting input is a virtual ground, so there is no common-mode swing and no dependence on the op-amp's output impedance for stopband attenuation. Preferred over Sallen-Key for Q above 1, stopband attenuation above 40 dB, and single-supply designs where the non-inverting input can be biased at a fixed mid-rail. Input impedance is $R_1$.

Multiple-feedback band-pass

Figure 13. Multiple-feedback band-pass.

$$f_0 = \frac{1}{2\pi C}\sqrt{\frac{R_1 + R_3}{R_1 R_2 R_3}}, \qquad Q = \frac{1}{2}\sqrt{\frac{R_2 (R_1 + R_3)}{R_1 R_3}}, \qquad A_0 = -\frac{R_2}{2 R_1} \quad (C_1 = C_2 = C)$$

$R_3$ sets $f_0$ nearly independently of Q and gain, which makes the topology tunable. The figure gives $f_0$ = 1.67 kHz, Q = 5.2, mid-band gain of 5. Q above about 20 requires excessive GBW and component precision; use a state-variable or biquad topology for higher Q. The op-amp needs GBW greater than about $20 \times Q \times A_0 \times f_0$.

Integrator

Figure 14. Integrator with DC gain limit.

$$V_{out} = -\frac{1}{R_1 C_f} \int V_{in}\, dt \quad \text{(above } f_{DC}\text{)}, \qquad f_{DC} = \frac{1}{2\pi R_f C_f}, \qquad f_{unity} = \frac{1}{2\pi R_1 C_f}$$

Without $R_f$, offset and bias current integrate to the rail (error 18). With $R_f$, DC gain is $-R_f/R_1$ and the circuit is a first-order low-pass with integration behavior between $f_{DC}$ and the op-amp's bandwidth. The figure gives DC gain -100, $f_{DC}$ = 15.9 Hz, and unity-gain frequency 1.59 kHz. Use a low-leakage capacitor (C0G, polypropylene, PPS) and a low-bias-current amplifier for long time constants. Use: active filters (state-variable), ramp generators, control loops (PI compensation), charge measurement.

Differentiator

Figure 15. Differentiator with gain limiting.

$$V_{out} = -R_f C_1 \frac{dV_{in}}{dt} \quad \text{for } f \ll f_1, \qquad f_1 = \frac{1}{2\pi R_s C_1}, \qquad f_2 = \frac{1}{2\pi R_f C_f}$$

$R_s$ and $C_f$ convert the ideal differentiator into a band-limited one: gain rises at 20 dB/decade up to $f_1$, is flat at $-R_f/R_s$ between $f_1$ and $f_2$, and falls above $f_2$. The figure places both at 159 kHz with a maximum gain of 100. Without these elements the circuit amplifies high-frequency noise without limit and is unstable (error 19). Use: rate-of-change detection, PID derivative term, edge detection. In practice the differentiator is avoided where an alternative exists, because it amplifies noise by design.

Transimpedance amplifier

Figure 16. Transimpedance amplifier for a photodiode.

$$V_{out} = I_{PD} R_f, \qquad f_{-3dB} = \frac{1}{2\pi R_f C_f}$$

The photodiode's capacitance $C_D$ (tens of pF to nF) at the inverting input, together with the op-amp's input capacitance, forms a pole with $R_f$ that produces noise-gain peaking and instability. $C_f$ adds a zero that restores phase margin. For 45° phase margin:

$$C_f = \sqrt{\frac{C_{in}}{2\pi R_f \cdot GBW}}$$

where $C_{in} = C_D + C_{op-amp}$. Larger $C_f$ gives more margin and less bandwidth. The figure gives 1 V per µA with 80 kHz bandwidth. Noise gain rises at high frequency to $1 + C_{in}/C_f$, which amplifies the op-amp's voltage noise; this is the dominant noise term in wideband TIAs, so low $e_n$ and low $C_{in}$ matter more than low $I_B$. Photovoltaic mode (zero bias, as drawn) gives lowest dark current; reverse bias reduces $C_D$ and raises bandwidth at the cost of dark current. Use a JFET or CMOS input amplifier for $R_f$ above about 100 kΩ, and a guard ring for $R_f$ above 10 MΩ. Use: photodiodes, photomultipliers, ion chambers, any current-output sensor.

Voltage-controlled current sink

Figure 17. Voltage-controlled current sink.

$$I_{out} = \frac{V_{ctl}}{R_s}$$

The op-amp drives the MOSFET gate until the voltage across $R_s$ equals $V_{ctl}$, so the load current is independent of the load and of the MOSFET's characteristics. Constraints: the op-amp output must reach $V_{GS}$ + $V_{ctl}$, the MOSFET needs $V_{DS}$ above its saturation voltage at the load current, and the op-amp's input range must include $V_{ctl}$ down to zero on a single supply if zero current is required. The MOSFET's gate capacitance forms a pole with the op-amp's output impedance; a series gate resistor of 100 Ω to 1 kΩ and a small capacitor from the op-amp output to its inverting input stabilize the loop. $R_s$ dissipates $I^2 R_s$; its temperature coefficient sets the current accuracy. Use: electronic loads, LED drivers, precision current sources, battery test.

Precision half-wave rectifier

Figure 18. Precision inverting half-wave rectifier.

$$V_{out} = -\frac{R_f}{R_1} V_{in} \text{ for } V_{in} < 0, \qquad V_{out} = 0 \text{ for } V_{in} > 0$$

The diode forward voltage is inside the feedback loop, so the output responds to inputs far below 0.6 V. When $V_{in}$ is positive, D2 conducts and holds the summing node at a virtual ground while D1 is off and $V_{out}$ is 0 through $R_f$. When $V_{in}$ is negative, D1 conducts and the circuit is an inverting amplifier. At the zero crossing the op-amp output must slew through $2 V_F$ with the loop open, which limits speed; use a fast amplifier and Schottky diodes. A full-wave rectifier is this stage summed with the input at gain 2 in a second inverting stage. Use: AC measurement, envelope detection, absolute value.

Comparator with hysteresis

Figure 19. Non-inverting comparator with hysteresis and open-drain pull-up.

$$V_{TH} = V_{ref}\left(1 + \frac{R_1}{R_2}\right) - V_{OL}\frac{R_1}{R_2}, \qquad V_{TL} = V_{ref}\left(1 + \frac{R_1}{R_2}\right) - V_{OH}\frac{R_1}{R_2}$$ $$\text{Hysteresis} = (V_{OH} - V_{OL}) \frac{R_1}{R_2}$$

Positive feedback through $R_2$ shifts the threshold after each transition, so noise smaller than the hysteresis band produces a single clean edge. The figure gives 0.5 V of hysteresis with a 5 V output swing. U1 is a comparator, not an op-amp (error 26). Open-drain comparators need the pull-up; push-pull comparators do not. The output logic levels enter the threshold equations, so a pull-up to a different rail than expected moves the thresholds. Use: level detection, zero-crossing detection, relaxation oscillators, window comparators.

Rail splitter

Figure 20. Buffered mid-supply reference.

$$V_{mid} = V_{CC} \frac{R_2}{R_1 + R_2}$$

The buffer provides a low-impedance virtual ground for single-supply circuits. It must source and sink the total current returned to the virtual ground by every stage that references it, so its output current rating sets the limit. $C_1$ filters the divider's noise and supply ripple. A large capacitor directly on the buffer output destabilizes it (error 13); if a low-impedance reference at high frequency is required, isolate the output capacitor with a small resistor. The TLE2426 is a dedicated part for this function. Use: single-supply audio and sensor chains, biasing multiple AC-coupled stages from one reference.

Capacitive load isolation

Figure 21. Non-inverting amplifier with in-loop capacitive load compensation.

$R_{iso}$ separates the load capacitance from the op-amp output. $C_f$ closes the loop at high frequency directly from the op-amp output, before $R_{iso}$, so the load pole is outside the loop where it matters for stability. $R_f$ closes the loop at DC and low frequency from the load side, so the DC accuracy is unaffected by the drop across $R_{iso}$. Design $R_f C_f$ to be about one to three times $R_{iso} C_L$. The simpler alternative is $R_{iso}$ alone with $R_f$ taken from the op-amp output, which is stable but adds $R_{iso}$ to the output impedance. Use: driving cables, MOSFET gates, ADC inputs, long traces, and any load above the datasheet's capacitive load limit.

ADC driver

Figure 22. Op-amp driving a SAR ADC through an RC filter.

$C_{flt}$ supplies the charge that the ADC's sampling capacitor $C_{SH}$ draws at the start of acquisition, so the amplifier sees an average load rather than a step. $R_{flt}$ isolates the amplifier from $C_{flt}$ for stability and forms an anti-aliasing pole. Design rules:

• $C_{flt} \geq 20 \times C_{SH}$, so the voltage droop when the sampling capacitor connects is below 1 LSB at the ADC's resolution.
• $R_{flt} C_{flt}$ short enough that the node settles to the required resolution within the acquisition time: $t_{acq} \geq R_{flt} C_{flt} \times \ln(2^{N+1})$ for N bits, which is about 12 time constants at 16 bits.
• $R_{flt}$ between 10 and 50 Ω for most SAR converters; larger values increase distortion from the ADC's non-linear input current.
• The amplifier must remain stable with $C_{flt}$ through $R_{flt}$. Check the datasheet's capacitive load plot at that isolation resistance.
• The ADC datasheet's recommended driver circuit takes precedence over these rules.

The figure gives a 7.96 MHz corner and suits a 1 MSPS, 16-bit converter with a 10 to 20 pF sampling capacitor.

Inverting level shifter

Figure 23. Inverting attenuator with level shift for a single-supply ADC.

$$V_{out} = V_{ref}\left(1 + \frac{R_f}{R_1}\right) - \frac{R_f}{R_1} V_{in}$$

The reference voltage on the non-inverting input is amplified by the noise gain and the signal by the inverting gain, so a bipolar signal is scaled and offset into a unipolar range in one stage. The figure maps ±10 V into 0 to 3.3 V: $R_f/R_1$ = 0.165 and $V_{ref}$ = 1.416 V. Because the configuration is inverting, the op-amp inputs sit at $V_{ref}$ regardless of the ±10 V input, so a 5 V single-supply amplifier handles it. The output must reach both ends of the ADC range, which requires a rail-to-rail output or a supply with headroom. $V_{ref}$ must come from a low-impedance source. Use: interfacing bipolar sensors and function generators to single-supply ADCs.

Input protection

Figure 24. Series resistor with clamp diodes.

$R_s$ limits the current into the clamp diodes and into the amplifier's internal ESD structure to a safe value: $I = (V_{fault} - V_{CC} - V_F) / R_s$. D1 and D2 clamp the input to one diode drop outside the rails; Schottky diodes (BAT54S) clamp below the internal diodes' forward voltage so that the internal structure never conducts. Costs: $R_s$ adds thermal noise and converts bias current to offset, and the diodes' leakage (nA for silicon, µA for Schottky at temperature) adds to the bias current. The supply rails must be able to absorb the clamp current; a rail with no load and a diode-clamped input can be pumped above its regulation voltage. Use: any input that connects to the outside world or that can be driven before the supply is present.

Part selection

By input stage technology

By application

Selection order

1. Supply voltage and whether the signal requires rail-to-rail input, rail-to-rail output, or both. This eliminates most of the table.
2. Source impedance, which selects the input technology by comparing $e_n$ against $i_n R_s$ and $\sqrt{4kTR_s}$.
3. Bandwidth and slew rate from the highest signal frequency and amplitude, with a factor of 10 to 100 margin on GBW for filters and precision gain stages.
4. DC accuracy: offset, drift, and bias current against the error budget, at the operating temperature rather than 25 °C.
5. Load: output current, capacitive load, and short-circuit behavior.
6. Stability: minimum stable gain and the capacitive load plot.
7. Package, quiescent current, price, and availability, in that order only after the above are satisfied.

Limitations of this document

• Design equations are ideal-op-amp results. They hold when the op-amp's GBW exceeds the circuit's highest frequency of interest by a factor of 10 or more and the loop gain at that frequency is above about 40 dB.
• Filter equations assume ideal, exact component values. Standard values and tolerances shift $f_0$ and Q; simulate with tolerances before committing to a design.
• Parameter ranges in the tables are typical of each class, not guaranteed for any part. The part numbers are representative and should be checked for current availability, and their datasheets take precedence over anything stated here.
• Stability rules are first-order guidance. Any circuit with a capacitive load, a large feedback resistor, or a decompensated amplifier should be verified by simulation of the loop gain or by measuring overshoot on the bench.