ADC Sampling and Analog Front-End Design

Sampling fundamentals

A signal sampled at rate $f_s$ is represented without ambiguity only if its spectrum is confined to a band of width less than $f_s/2$. Any content at frequency $f$ outside that band appears in the sampled data at the alias frequency

and is indistinguishable from a real signal at $f_{alias}$. No later processing can separate them.

Three points follow from the equation that are often missed:

• Bandwidth, not highest frequency, sets the requirement. The signal band includes every source of energy that reaches the ADC: the signal, the sensor's and amplifier's noise out to their own bandwidths, switching supply ripple, and radio-frequency pickup. An amplifier with a 1 MHz noise bandwidth sampled at 10 kHz with no filter folds its noise 200 times over, raising the floor by 23 dB. The anti-alias filter defines the noise bandwidth as well as the signal bandwidth.
• The first frequency that folds onto the passband edge is $f_s - f_{pass}$, not $f_s/2$. Content between $f_s/2$ and $f_s - f_{pass}$ folds into the transition band, which lies outside the passband. This matters whenever a digital filter follows the ADC, because that content can still be removed. It is the basis of the oversampling strategy below.
• The ADC's analog input bandwidth is separate from its sample rate. A SAR converter's track-and-hold may have a 50 MHz bandwidth at a 1 MSPS sample rate. That permits bandpass sampling of signals above $f_s/2$, and it also means high-frequency interference reaching the input aliases with full amplitude.

The oversampling ratio is defined relative to the signal bandwidth $B$:

Resolution, noise, and ENOB

The number of bits in the part number describes the code width, not the accuracy. The quantities that describe what the converter delivers are:

Ideal SNR for a full-scale sine with only quantization noise:

Noise sources in a real channel. The measured SNR is set by the root-sum-square of the following, referred to the ADC input:

• Quantization noise, LSB/√12 rms.
• ADC transition noise, specified as rms LSBs or as a code histogram width. High-resolution SAR and delta-sigma parts have several LSBs of transition noise; their effective resolution is what the datasheet's noise table says, not the code width.
• Sampling capacitor thermal noise, $\sqrt{kT/C}$: 20 µV rms at 10 pF, 6.4 µV at 100 pF, 2.0 µV at 1 nF. It is inherent to the sampling operation and is why small-capacitor SAR inputs cannot reach 20-bit noise floors.
• Driver amplifier and filter resistor noise integrated over the noise bandwidth of the anti-alias filter.
• Reference noise, which multiplies the signal and appears as noise proportional to input amplitude.
• Sampling clock jitter, which converts to voltage noise proportional to input slew rate.

Clock jitter. For a full-scale sine at $f_{in}$ and rms jitter $t_j$:

Maximum rms jitter for jitter noise to equal the ideal quantization noise:

A microcontroller timer or PLL output has jitter in the range of 100 ps to several ns. For inputs above a few kHz at 16 bits, the sampling clock must come from a low-jitter source, and the conversion start must be triggered by hardware, not by software in an interrupt handler.

Noise-free resolution. With rms noise of $\sigma$ LSBs, the effective resolution is $N - \log_2 \sigma$ bits and the noise-free (flicker-free) resolution, using the 6.6σ peak-to-peak convention, is $N - \log_2(6.6\,\sigma)$ bits. A 24-bit converter with 20 LSB rms noise delivers 19.7 effective bits and 17 noise-free bits.

Averaging and oversampling gain. Averaging $M$ samples reduces white noise by $\sqrt{M}$, adding $0.5 \log_2 M$ bits: 2 bits for 16 samples, 4 bits for 256. This requires the noise to be at least about 1 LSB rms and uncorrelated between samples. Below 1 LSB of noise the quantizer is deterministic and averaging returns the same code; dither (added noise of about 1 LSB rms, or the ADC's own noise) restores the gain. DNL and 1/f noise set the limit.

DC accuracy is a separate budget. Offset, gain error, INL, and their temperature drift are not reduced by averaging or by oversampling. They are reduced by calibration against a reference, by ratiometric measurement, and by choosing a converter with the required INL. A 16-bit converter with 4 LSB INL is a 14-bit converter for absolute measurements and a 16-bit converter for detecting small changes.

ADC architectures

SAR and pipeline converters sample instantaneously and the anti-alias problem is entirely external. Delta-sigma converters oversample internally and include a decimating digital filter, which moves most of the alias rejection into the part, but the modulator still samples at its own rate and the analog RC in front of it must attenuate content near multiples of that rate.

Sample rate and filter strategy

Three strategies exist. The choice determines the anti-alias filter order more than any other decision.

Nyquist-rate sampling. $f_s$ is 2.2 to 3 times the signal bandwidth. The transition band from $f_{pass}$ to $f_s - f_{pass}$ is narrow, and the analog filter alone must reach the full required attenuation inside it.

Figure 2. Nyquist-rate frequency plan. The analog filter must reach the required attenuation by the first frequency that folds onto the passband edge.

Oversampling with a digital filter. $f_s$ is 8 to 64 times the signal bandwidth. The transition band is wide and a second-order or fourth-order analog filter reaches the required attenuation by $f_s - f_{pass}$. A digital filter then sets the sharp passband edge, removes the content between $f_{pass}$ and $f_s - f_{pass}$, and the data is decimated to the final rate. The digital filter has no component tolerance, no drift, linear phase if FIR, and a transition band as narrow as the computation budget permits.

Figure 3. Oversampled frequency plan. The analog filter handles only the image around the sample rate. The digital filter removes the bands that would fold into the passband after decimation.

Delta-sigma. The converter implements the oversampling strategy internally. The external filter is a single RC, and the design work moves to choosing the output data rate, understanding the internal filter's droop and settling, and handling multiplexed channels.

Selection rules:

• Below about 100 kHz bandwidth with a single channel and 16 bits or more, delta-sigma is the default.
• Multiple channels that must be sampled simultaneously, or a bandwidth above 100 kHz, favor SAR with oversampling and a digital filter.
• Nyquist-rate sampling is the choice only when the converter's maximum rate is the constraint, and then the filter is usually an integrated switched-capacitor or elliptic design rather than discrete op-amp stages.

Anti-alias filter design

Digital filtering and decimation

The digital filter after an oversampled converter has three jobs: set the passband edge, attenuate the bands that will fold into the passband when the data is decimated, and correct droop introduced by the analog stages or by a preceding CIC stage.

Fold bands after decimation. Decimating by $M$ to $f_{out} = f_s / M$ folds every band $k f_{out} \pm f_{pass}$ for $k$ = 1 to $M - 1$ into the passband. The digital filter must attenuate all of them to the required level before decimation. The band around $f_s$ itself is the analog filter's responsibility. A filter designed only for the passband edge, without checking its stopband at those fold bands, is the most common error in this stage.

Practical rules:

• Estimate FIR length with the Kaiser formula $N \approx (A - 8) / (2.285\, \Delta\omega)$, where $\Delta\omega$ is the transition width in radians per sample. A narrow transition band at a high sample rate produces long filters; decimate in stages (CIC or half-band first, then a short FIR at the lower rate) to keep computation low.
• A CIC stage's droop at the passband edge is compensated by an inverse-sinc term in the following FIR.
• Group delay of a linear-phase FIR is half its length in samples. For a control loop this latency must be counted in the loop.
• The internal filters of delta-sigma converters are sinc filters of order 3 to 5, with nulls at multiples of the output data rate. Their droop at the passband edge is significant: for a sinc³ filter, -0.17 dB at $f_{out}/16$, -0.67 dB at $f_{out}/8$, -2.7 dB at $f_{out}/4$, and -11.8 dB at $f_{out}/2$. Either the output rate is set well above twice the signal bandwidth, or a droop-compensating filter follows, or the part is configured for a wideband (flat) filter mode.
• Sinc filter nulls are used to reject mains interference: an output rate of 10 SPS places nulls at 50 Hz and 60 Hz and their harmonics.
• After a step change in the input, or a channel change, a sinc filter of order $k$ needs $k$ output periods to settle fully. Multiplexed delta-sigma channels therefore run at $1/k$ of the nominal rate unless the part has a fast-settling mode.

Input structure and driver

The converter's input must be driven by a source that settles to the required resolution within the acquisition time. For a SAR converter, the sampling capacitor $C_{SH}$ (typically 5 to 50 pF) connects to the input at the start of acquisition and draws a charge step. The RC network at the input supplies that charge and isolates the driver:

• $C_{flt} \geq 20\, C_{SH}$ so the voltage step when the capacitor connects is below 1 LSB.
• Settling to $N$ bits requires $t_{acq} \geq \tau \ln(2^{N+1})$, with $\tau = R_{flt} C_{flt}$: 9.0τ at 12 bits, 11.8τ at 16 bits, 14.6τ at 20 bits.
• $R_{flt}$ between 10 and 50 Ω for most SAR converters. The converter's input current is non-linear with input voltage, and a larger resistor converts that into distortion.
• The driver amplifier must be stable with $C_{flt}$ through $R_{flt}$, and its bandwidth must be high enough to recover from the kickback within the acquisition time. Datasheets specify this combination; the converter's recommended driver takes precedence over these rules.

Differential inputs. A differential input rejects common-mode interference, cancels even-order distortion, and doubles the full-scale range for a given supply. The input filter uses a differential capacitor across the pins with a smaller capacitor from each pin to ground:

Figure 4. Differential ADC input filter. The differential capacitor is at least ten times the common-mode capacitors so that mismatch between the two common-mode capacitors does not convert common-mode noise into a differential signal.

The common-mode capacitors are matched to each other and are small enough that their tolerance does not matter, because the differential capacitor dominates the differential corner. The corner frequencies are $1/(2\pi \cdot 2 R_s C_{diff})$ for the differential signal and $1/(2\pi R_s C_{cm})$ for common mode. The driver, usually a fully differential amplifier, sets the output common-mode voltage to the converter's required value through its VOCM pin, which is fed from the converter's common-mode output or from the reference divided by two.

Single-ended converters accept the signal on one pin against ground and lose the common-mode rejection. Pseudo-differential converters sample the signal pin against a sense pin that carries the signal ground, which removes ground offset between the source and the converter but not common-mode noise above DC.

Reference. The reference sets the full-scale voltage, and its noise, drift, and load response appear directly in the result. A SAR converter draws a current pulse from the reference at each conversion; the reference decoupling capacitor (typically 1 to 22 µF, per the datasheet) must supply it without droop, and the reference must recover between conversions. Reference noise is measured as a fraction of full scale, so it matters most for large signals. For ratiometric sensors (bridges, potentiometers), the sensor excitation and the converter reference come from the same source so that reference drift cancels.

Multiplexed and multi-channel systems

• Each channel has its own anti-alias filter ahead of the multiplexer, as stated above. The per-channel filter's output impedance and the multiplexer's on-resistance together must drive the post-multiplexer RC within the acquisition time.
• The multiplexer's charge injection produces a voltage step on the selected channel's filter capacitor. A larger capacitor reduces the step but lengthens settling; the usual compromise is a capacitor of a few nF and a settling time constant of a few hundred ns.
• Crosstalk: with the multiplexer off, an adjacent channel couples through the off-capacitance and the shared post-multiplexer node. Specify the multiplexer's off-isolation at the highest frequency present on any channel, after that channel's filter.
• Channel sequencing: a channel that switches from a full-scale signal to a small one exposes the settling error; measure settling with the worst-case step, not with similar signals on adjacent channels.
• Multiplexing a delta-sigma converter: each channel change requires the digital filter to settle, which takes several output periods. The effective per-channel rate is the output rate divided by the channel count and by the filter settling count. Parts with per-channel settling modes or with multiple converters on one die avoid this.
• Simultaneous sampling: applications that compare phase or timing between channels (power measurement, motor current sensing, arrays of sensors) require converters with one track-and-hold per channel, or one converter per channel with a shared clock. A single multiplexed converter introduces a time skew of one conversion period per channel, which is 3.6° at 50 Hz for a 200 µs skew.

Design errors

1. Filtering to $f_s/2$ instead of to $f_s - f_{pass}$. The alias requirement is at the fold frequency. Filtering to $f_s/2$ leaves the band between $f_s/2$ and $f_s - f_{pass}$ underattenuated, which folds into the transition band and, in a Nyquist-rate design, into the passband edge.
2. Bandwidth defined by the signal alone. The amplifier noise bandwidth and the sensor's own bandwidth fold into the passband and raise the noise floor. Correction: set the anti-alias filter as the element that defines the channel noise bandwidth, and budget the folded noise.
3. Anti-alias filter after the multiplexer. The filter cannot both settle within the acquisition time and provide alias rejection. Correction: per-channel filters before the multiplexer.
4. Class 2 ceramic capacitors in the filter. Voltage coefficient, temperature coefficient, and piezoelectric effects produce distortion and corner shift. Correction: C0G, polypropylene, or PPS.
5. Insufficient op-amp bandwidth for the filter stage. The response departs from the design near $f_c$, with peaking or premature roll-off. Correction: GBW at least 20 times $f_c \times Q$.
6. Sallen-Key used for high attenuation. The op-amp's rising output impedance lets high-frequency content feed through the feedback capacitor. Correction: MFB topology, or an RC after the Sallen-Key stage.
7. Input RC sized as the anti-alias filter. A large RC at the converter pin cannot settle in the acquisition time and produces a signal-dependent settling error, which appears as gain error and distortion. Correction: separate the anti-alias filter from the settling RC.
8. Input RC omitted. The driver sees the sampling capacitor's charge step directly, rings, and does not settle. Correction: the RC per the converter datasheet.
9. Reference decoupling per a generic rule rather than the datasheet. The reference droops during conversion and the result acquires a code-dependent gain error. Correction: the capacitor value and placement from the datasheet, and a reference with adequate transient response.
10. Software-triggered conversions. Interrupt latency adds jitter of hundreds of nanoseconds to microseconds. At 16 bits this limits the usable input frequency to a few hundred Hz. Correction: hardware timer trigger and DMA.
11. Digital filter stopband not checked at the fold bands. The filter passes the wanted band and attenuates the transition band but not the bands at multiples of the output rate. Correction: verify attenuation at $k f_{out} \pm f_{pass}$ for all $k$ up to $M - 1$.
12. Averaging with noise below 1 LSB. The converter returns the same code repeatedly and averaging adds nothing. Correction: dither, or use a converter with noise at or above 1 LSB rms so that averaging is effective.
13. Sinc filter droop ignored. A delta-sigma converter run with the output rate at only twice the signal bandwidth attenuates the passband edge by more than 10 dB. Correction: output rate at least 8 to 16 times the bandwidth, or droop compensation, or the part's flat filter mode.
14. Multiplexed delta-sigma without settling. Data after a channel change is a blend of the previous and current channels. Correction: discard the settling conversions or use a part with per-channel settling.
15. Phase mismatch between channels neglected. Filter component tolerance produces channel-to-channel phase differences that corrupt power or impedance measurements. Correction: tighter tolerance, higher filter corner, or digital calibration.
16. Filter capacitor grounds returned to a noisy ground. The filter's ground reference is the converter's analog ground; a capacitor returned elsewhere injects the difference voltage into the signal. Correction: capacitor returns at the converter's analog ground pin.
17. Overload recovery not considered. An out-of-band interferer that saturates the filter op-amp produces a recovery transient inside the passband. Correction: a passive pre-filter before the active stages, and an amplifier with specified overload recovery.
18. Mains interference handled only by filtering. Mains harmonics inside the passband cannot be filtered without removing signal. Correction: sinc nulls at the mains frequency, sampling synchronous with the mains period and averaging over whole periods, or differential inputs with high common-mode rejection.
19. Undersampling without a bandpass filter. Bandpass sampling requires that everything outside the wanted band be attenuated, including the baseband. A low-pass filter does not achieve this. Correction: bandpass anti-alias filter, and a converter with track-and-hold bandwidth and jitter adequate for the carrier frequency, not just the signal bandwidth.
20. Test with a clean signal generator only. A laboratory signal source has no out-of-band content, so aliasing is not exercised. Correction: verification with tones placed at the fold frequencies, and with the real sensor and cabling.

Design procedure

1. Signal specification. Bandwidth $B$, amplitude range, and whether the information is in the DC value, the time-domain waveform, or the spectrum. This determines flatness, phase, and settling requirements.
2. Dynamic range. Required SNR and DC accuracy, separately. Convert SNR to a converter resolution with 2 to 4 bits of margin for transition noise, driver noise, and reference noise.
3. Out-of-band inventory. The amplifier and sensor noise bandwidth, known interferers with their frequencies and amplitudes, and the largest signal that can appear at the input under fault conditions.
4. Architecture. Delta-sigma for precision at low bandwidth on few channels; SAR with oversampling and a digital filter for multi-channel or wideband; pipeline above about 10 MSPS.
5. Sample rate. Choose $f_s$ from the strategy table. Compute $f_{stop} = f_s - f_{pass}$ and $A_{stop}$.
6. Analog filter. Choose $f_c$ from the droop table, compute the order from the transition ratio, choose the response type from the application, and select the topology. Check op-amp GBW.
7. Digital filter. Passband edge, stopband at the fold bands, decimation factor, structure (CIC plus FIR, half-band chain, or single FIR), and latency.
8. Input drive. Input RC from the converter datasheet, driver amplifier stability and settling, differential or single-ended, common-mode voltage.
9. Reference and clock. Reference noise and decoupling per the datasheet; sampling clock jitter against the jitter table; hardware triggering.
10. Multi-channel. Per-channel filters, multiplexer settling and crosstalk, simultaneous sampling where phase matters.
11. Budget. Root-sum-square of the noise sources; separate sum of the DC error sources; comparison with the requirement.
12. Verification. Fold-frequency tone test, passband sweep, noise floor with shorted input, overload test, and a test with the real source.

Worked example

Requirement: a sensor with 1 kHz bandwidth, 16-bit dynamic range (98 dB), time-domain waveform fidelity, four channels sampled simultaneously.

Nyquist-rate SAR. $f_s$ = 2.5 kHz. $f_{stop}$ = 1.5 kHz. With $f_c$ = 1.27 kHz for 0.1 dB droop at eighth order, the transition ratio is 1.18 and the Butterworth order required for 96 dB is 66. Not feasible with discrete stages. An elliptic filter of tenth order or a switched-capacitor filter could approach it, at the cost of ripple, phase distortion, and component sensitivity incompatible with waveform fidelity. Rejected.

Oversampled SAR with digital filter. $f_s$ = 40 kHz per channel, four-channel simultaneous-sampling SAR. $f_{stop}$ = 39 kHz. Fourth-order Butterworth with $f_c$ = 1.6 kHz: droop at 1 kHz is 0.1 dB, transition ratio is 24.4, attenuation at 39 kHz is 111 dB, exceeding the 96 dB requirement. Implementation: two MFB stages with Q of 0.54 and 1.31 (fourth-order Butterworth), 1% resistors, 1% C0G capacitors, op-amp GBW above 1 MHz. Digital filter: decimate by 4 with a CIC, then a linear-phase FIR at 10 kHz with passband to 1 kHz, stopband from 1.5 kHz at 96 dB with inverse-sinc droop correction, then decimate by 4 to a 2.5 kHz output rate. FIR length is about 120 taps at 10 kHz, compared with about 490 taps if implemented directly at 40 kHz. Oversampling by 16 adds 12 dB of processing gain against white converter noise. Group delay is about 60 output samples, 24 ms; acceptable for recording, to be evaluated if the data feeds a control loop. Selected.

Delta-sigma. Four-channel simultaneous-sampling delta-sigma with a 16 kHz output rate and a sinc³ filter, modulator at 1 MHz. Droop at 1 kHz is 0.17 dB, acceptable. External filter: single RC at 50 kHz per channel, per the datasheet. Simplest analog design, but with a 16 kHz output rate the data must still be filtered and decimated digitally to reach the 2.5 kHz rate, and the sinc³ group delay of about 190 µs plus the decimation filter must be counted. Also acceptable; the choice between this and the SAR design is made on the converter's cost and availability and on the digital resources.

Limitations of this document

• The filter order and droop tables are for Butterworth responses. Other responses require their own tables or a filter design tool.
• Noise and jitter figures assume full-scale sine inputs and white noise. Signals with lower amplitude or 1/f-dominated noise require their own analysis.
• Converter input models vary. The settling rules here are first-order approximations; the converter datasheet's driver recommendations and the manufacturer's tools (TI Precision Labs, ADI's analog filter and driver tools) take precedence.
• Values quoted for typical parts (sampling capacitance, reference decoupling, jitter of clock sources) are representative ranges and must be confirmed against the actual parts.