MOSFET Crash Course

Device basics

A MOSFET is a voltage-controlled resistor with a threshold. Gate-to-source voltage above the threshold forms a conducting channel between drain and source; the channel resistance falls as the gate voltage rises further. No steady-state gate current flows, but the gate is a capacitor of several nanofarads, and charging and discharging it at high frequency is a significant current.

Operating regions. For an N-channel device with $V_{GS} > V_{GS(th)}$:

The naming is the reverse of a BJT's: a MOSFET in "saturation" is the region of high dissipation, and the "linear" region is the fully-on switch state. Power dissipation is $V_{DS} I_D$ in either region; in the ohmic region $V_{DS}$ is small by design, in saturation it is not.

Body diode. The source metallization shorts the body to the source, which places a PN diode from source to drain in every N-channel device. It conducts when the drain goes below the source, which is the normal state of the low-side switch in a synchronous converter during dead time. It is slow (reverse recovery charge $Q_{rr}$ of tens to hundreds of nC) and its forward drop is 0.7 to 1.2 V. It cannot be removed and it cannot be relied on as a rectifier without accounting for its recovery.

P-channel. Complementary structure, conducts with the gate pulled below the source. Simplifies high-side drive from a ground-referenced signal at low voltage. For the same die area, $R_{DS(on)}$ is two to three times higher than N-channel because hole mobility is lower, so P-channel devices are used where drive simplicity outweighs conduction loss: load switches, reverse-polarity protection, and low-current high-side switches.

Structures. Planar devices have the gate on the surface and a wide, thermally stable channel; they have higher $R_{DS(on)}$ per area and better linear-mode capability. Trench devices bury the gate in a trench to pack cells densely, which gives lower $R_{DS(on)}$ and lower charge, and worse linear-mode behavior. Superjunction devices (above 500 V) use charge balance to reduce on-resistance in the drift region and have a highly non-linear output capacitance. SiC MOSFETs extend the range to 1.2 kV and above with fast switching and a body diode of high forward drop; GaN HEMTs have no body diode and no reverse recovery, very low gate charge, and a gate that tolerates only a narrow voltage range.

Datasheet parameters

Every parameter on the first page is specified at conditions that flatter the part. The conditions are in the test-conditions column and the graphs.

Temperature coefficients that matter. $R_{DS(on)}$ has a positive temperature coefficient, which makes paralleled devices share current in the ohmic region: the hotter device carries less. $V_{GS(th)}$ has a negative coefficient and $g_{fs}$ at low current has a positive one, so in the saturation region a hotter region of the die carries more current. That is the origin of thermal instability in linear operation and of the zero-temperature-coefficient point (ZTC) discussed under SOA.

Conduction and switching losses

Total loss in a switching device is the sum of five terms. Which one dominates determines which datasheet parameter to optimize.

Conduction loss.

For a switch carrying current $I$ with peak-to-peak ripple $\Delta I$ at duty cycle $D$: $I_{rms}^2 = D \left( I^2 + \Delta I^2 / 12 \right)$. Use the hot $R_{DS(on)}$ and iterate with the thermal calculation, because $R_{DS(on)}$ depends on the temperature that the loss produces.

Switching loss. During each transition, voltage and current overlap. For a clamped inductive load (every hard-switched converter), the current transfers first and then the voltage, or the reverse, so the overlap is a triangle in each transition:

The transition times are set by the gate charge and the gate current, not by the datasheet's switching-time table:

where $Q_{GS2}$ is the portion of $Q_{GS}$ between the threshold and the plateau (roughly half of $Q_{GS}$ when not specified separately), and $R_{G,total}$ is the sum of the driver output resistance, the external gate resistor, and the device's internal gate resistance $R_{G(int)}$.

Output capacitance loss. At each turn-on, the energy stored in $C_{OSS}$ is dissipated in the channel:

$C_{O(er)}$ is the energy-related effective capacitance from the datasheet; the small-signal $C_{OSS}$ at 25 V underestimates it. In a half bridge, the turning-on device also discharges the opposing device's $C_{OSS}$, so both appear in the loss of the device that turns on. In soft-switched (ZVS) converters this term is recovered rather than dissipated, and the relevant figure becomes $Q_{oss}$ or $C_{O(tr)}$.

Gate drive loss. Charging the gate to $V_{drive}$ and discharging it dissipates $Q_G V_{drive} f_{sw}$ per device. It is dissipated in the driver and the gate resistors, not in the MOSFET channel, but it is drawn from the bias supply and it heats the driver. At 500 kHz with 50 nC and 10 V, it is 0.25 W per device.

Body diode loss. In a synchronous rectifier, the body diode conducts during dead time: $P_{dead} = V_F I_D (t_{dead,on} + t_{dead,off}) f_{sw}$. Its reverse recovery then produces a loss of about $Q_{rr} V_{IN} f_{sw}$, dissipated in the device that turns on against it. Both terms grow with temperature.

Figure of merit. Conduction loss scales inversely with die area, and switching and capacitive losses scale with it, so for a given process there is an optimum die size for a given frequency and current. The product $R_{DS(on)} \times Q_G$ (or $R_{DS(on)} \times Q_{GD}$ for hard switching, $R_{DS(on)} \times Q_{oss}$ for resonant converters) compares processes independently of die size; a lower product is a better process. Between two parts on the same process, the lower $R_{DS(on)}$ part has the higher charge, and the loss calculation decides.

Figure 1. Switching waveforms for a clamped inductive load. Shaded intervals are the voltage and current overlap that produces switching loss. The gate voltage sits at the plateau while the drain voltage transitions.

Gate drive and the Miller plateau

The gate charge curve is the datasheet's most useful graph for switching design. It plots $V_{GS}$ against the charge delivered to the gate at a fixed drain current and supply voltage.

Figure 2. Gate charge curve. The plateau is the interval during which the gate current flows into the gate-drain capacitance while the drain voltage swings, and the gate voltage does not rise.

Three regions:

1. 0 to $Q_{GS}$. The gate-source capacitance charges. Nothing happens at the drain until $V_{GS(th)}$; between the threshold and the plateau the drain current rises to the load current.
2. $Q_{GS}$ to $Q_{GS} + Q_{GD}$, the Miller plateau. The drain current has reached the load current and the drain voltage falls. As it falls, the gate-drain capacitance must be charged through the full drain swing, and all the gate current goes into it. $V_{GS}$ stays at the plateau voltage, which is the gate voltage that supports the load current in saturation: $V_{plateau} \approx V_{GS(th)} + I_D / g_{fs}$. The plateau length in time is $Q_{GD} / I_G$, and it is the voltage transition time.
3. Above $Q_{GS} + Q_{GD}$. The device is in the ohmic region and further gate charge lowers $R_{DS(on)}$ toward its final value. Charge delivered above about 10 V on a standard device buys almost nothing.

The whole curve scales: $Q_{GD}$ is proportional to the drain voltage swing, and the plateau voltage rises with drain current.

Drive circuit. The gate driver is a low-impedance push-pull stage with a stated peak source and sink current, or equivalently an output resistance. The external gate resistor adds to it and to the internal gate resistance of the MOSFET.

Figure 3. MOSFET with its parasitic capacitances and gate drive loop. The gate-drain capacitance is the path by which drain transitions couple back into the gate.

Functions of the external gate resistor:

• It sets the switching speed, and therefore the trade between switching loss and EMI, ringing, and $dV/dt$ stress on other components.
• It damps the resonance between the gate capacitance and the loop inductance of the drive path. A gate loop with 10 nH and 3 nF resonates at 29 MHz with a characteristic impedance of 1.8 Ω; a resistor of about that value is the minimum for damping.
• Separate turn-on and turn-off paths (a diode across the resistor, or a driver with separate outputs) allow slow turn-on for EMI and fast turn-off for immunity.

Induced turn-on ($dV/dt$ turn-on, Miller shoot-through). When the drain of an off device slews upward, current $C_{GD} \, dV/dt$ flows through the gate-drain capacitance and must exit through the gate resistance to the driver's low output. The gate rises by approximately $C_{GD} \cdot dV/dt \cdot R_{G,total}$ (for slew durations short compared with the gate time constant, the voltage is closer to $V_{DS} \cdot C_{GD} / C_{ISS}$). If it reaches $V_{GS(th)}$ minimum at temperature, the device conducts while the opposing device is on. Defenses: a driver with low pull-down resistance, a separate small turn-off resistor, a Miller clamp (a driver transistor placed directly at the gate), negative gate bias at turn-off (standard for SiC), and a device with a low $Q_{GD} / Q_{GS}$ ratio and a high threshold.

Drive voltage. $R_{DS(on)}$ is specified at 10 V for standard devices and 4.5 V for logic-level devices, and the specification at any other voltage comes from the $R_{DS(on)}$ vs $V_{GS}$ curve. A 3.3 V microcontroller output driving a logic-level device gives a resistance well above the 4.5 V specification, at an undefined temperature coefficient, and often will not fully enhance the device at all at high temperature where the threshold has fallen but the transconductance has not risen enough. Use a gate driver, or a device specified at the available voltage. Drive voltage above 12 V produces no further reduction in $R_{DS(on)}$ on most parts and reduces the margin to the gate rating.

High-side drive. An N-channel high-side switch needs a gate voltage above its source, which sits at the switched node. Bootstrap drivers charge a capacitor from the bias supply while the switch node is low and use it to drive the gate when the node is high; they require the low side to turn on periodically to refresh the capacitor, and the maximum on-time is limited by the capacitor's leakage budget. Isolated or level-shifted drivers, or charge pumps (as in hot-swap controllers), remove that limit at higher cost.

Layout. The gate drive loop (driver, gate resistor, gate, source, back to the driver ground) must be small. A Kelvin source connection, available on packages with a separate source-sense pin, removes the common source inductance from the drive loop: without it, $L_S \, dI/dt$ during the current transition subtracts from the gate drive voltage and slows the switching, and the effect grows with current.

Safe operating area and linear-mode operation

The SOA graph gives the combinations of drain voltage, drain current, and pulse duration that the device survives with the case at 25 °C.

Figure 4. Safe operating area, log-log. Each pulse-width line is a constant-power line until thermal instability bends the DC line downward at high drain voltage.

Boundaries:

• $R_{DS(on)}$ limit. At low voltage the device is a resistor, and the current cannot exceed $V_{DS} / R_{DS(on)}$. The slope is +1 on log-log axes.
• Pulsed current limit. Horizontal line at $I_{DM}$, set by bond wires, metallization, and the package.
• Constant-power lines. For each pulse width, a slope of -1 line at the power that raises the junction to its maximum during that pulse. They are derived from $Z_{\theta JC}(t)$, and the DC line from $R_{\theta JC}$.
• Thermal instability limit. At high $V_{DS}$ and low $I_D$, the DC and long-pulse lines fall faster than constant power. The operating point is in saturation where the temperature coefficient of drain current is positive below the ZTC current: a hotter cell draws more current, heats further, and current concentrates in a hot spot that reaches the failure temperature while the average die temperature is well below it. This is the Spirito effect. It is worse in trench devices with high transconductance and dense cells, and worse at high voltage because the same power occurs at low current, far below the ZTC point. Datasheets for some trench devices draw the DC line as a calculated constant-power line and add a note, or omit it; a DC line drawn as straight constant power on a modern low-$R_{DS(on)}$ trench part is not to be trusted without a note saying it was measured.
• Breakdown voltage. Vertical line at $V_{(BR)DSS}$.

Reading and derating.

• All lines are for $T_C$ = 25 °C. Derate the permissible power linearly with case temperature: multiply by $(T_{J,max} - T_C) / (T_{J,max} - 25)$. At $T_C$ = 100 °C and $T_{J,max}$ = 175 °C, the factor is 0.5. The thermal instability region derates further than this, and some manufacturers provide SOA curves at elevated case temperature for linear-mode parts.
• Lines are for single pulses. For repetitive pulses, use $Z_{\theta JC}$ at the duty cycle, or the average power plus the single-pulse rise above it.
• Non-rectangular pulses (the triangular power pulse of a capacitor charge) are converted to an equivalent rectangular pulse of the same peak power and about half the duration for thermal purposes, or evaluated with a thermal simulation. The thermal instability limit is not captured by that conversion; check the peak voltage and current point against the line for the full pulse duration.
• Interpolate between pulse-width lines on the log-log plot.
• Design to the SOA with margin of at least 30 % in current at the operating voltage, because the curves are typical and the mechanism is a runaway.

Linear-mode applications. Hot-swap and inrush controllers, electronic loads, linear regulators and current sources, soft-start of capacitive loads, and active clamps all operate the device in saturation for milliseconds to continuously. For them:

• $R_{DS(on)}$ is nearly irrelevant to the stress; the energy that must be dissipated is set by the application. Charging a capacitor $C$ to voltage $V$ through a MOSFET dissipates $\tfrac{1}{2} C V^2$ in the MOSFET regardless of how slowly it is done, plus any load current drawn during the ramp times the remaining voltage.
• The lowest-$R_{DS(on)}$ trench device is the worst choice. Planar devices, older trench generations, and parts marketed for linear mode ("linear MOSFET", "hot-swap MOSFET", ASFET, L2 series) have measured DC SOA lines, lower transconductance at low current, and larger thermally stable cells.
• Paralleling devices in linear mode does not share current: the device with the lowest threshold takes it all. Separate source resistors of a few tens of millivolts at the operating current force sharing, at the cost of loss and gate drive complexity.
• The gate is driven slowly and the driver is a current source of microamps (a hot-swap controller's gate pin); the gate-source clamp, and the gate capacitance added to set the ramp rate, are part of the design.
• Transient thermal impedance and the SOA together, never $R_{\theta JA}$ alone, determine survival.

Selecting a MOSFET

1. Voltage. $V_{(BR)DSS}$ at 1.25 to 1.5 times the maximum steady-state voltage the device blocks, with the actual ringing measured or simulated. For a 12 V rail: 25 to 30 V. For 48 V with telecom transients: 100 V. For a 400 V bus: 600 to 650 V. Confirm $V_{GS}$ rating against the drive voltage plus ringing.
2. Function. Hard switching, soft switching, synchronous rectification, or linear mode. This chooses the loss terms and parameters that matter: $Q_{GD}$ and $Q_{rr}$ for hard switching, $Q_{oss}$ and $R_{DS(on)}$ for soft switching, $R_{DS(on)}$ and body diode for synchronous rectification, SOA for linear mode.
3. Loss estimate. Compute all loss terms at the design frequency and current with hot $R_{DS(on)}$. Compare candidate parts on total loss, not on $R_{DS(on)}$.
4. Thermal. Junction temperature from the total loss and the thermal path actually available: $R_{\theta JA}$ on the intended copper area, or $R_{\theta JC}$ plus the heat sink path. Target $T_J$ below 110 to 125 °C in operation for reliability; the 150 or 175 °C rating is a survival limit.
5. Gate drive. Drive voltage available, driver current, and the resulting switching times. Confirm $R_{DS(on)}$ at the drive voltage. Check induced turn-on for the off device in a bridge.
6. Package. Thermal resistance, source inductance, Kelvin source availability, current capability of the leads, and the board area. SO-8 and PowerPAK/DFN for low voltage; D2PAK, TO-220, TO-247 as current and voltage rise; top-side-cooled packages for heat sinks.
7. SOA and pulse ratings for any application that operates the device in saturation for more than a switching transition, or that must survive short circuits.
8. Body diode ($V_F$, $Q_{rr}$) for bridges and synchronous rectifiers. Consider a device with a fast body diode or an external Schottky in parallel.
9. Second-order. Avalanche rating where inductive spikes can reach breakdown; $dV/dt$ rating; ESD protection on the gate; automotive qualification if required.

Figures of merit to compare parts on a shortlist: $R_{DS(on)} Q_G$ for switching in general, $R_{DS(on)} Q_{GD}$ for hard-switched loss, $R_{DS(on)} Q_{oss}$ for resonant and ZVS converters, and the SOA current at the operating voltage for the DC or relevant pulse width in linear mode.

Datasheet misreadings

1. Continuous drain current used as a rating. It assumes the case at 25 °C. With $R_{\theta JA}$ of 40 °C/W and a 1.5 W budget, a device rated at 100 A carries 20 to 30 A. Correction: compute current from the thermal budget.
2. $R_{DS(on)}$ at 25 °C. The hot value is 1.5 to 2.5 times higher. Correction: read the normalized curve at the design junction temperature and iterate with the thermal calculation.
3. $R_{DS(on)}$ at the wrong gate voltage. The headline value is at 10 V; the circuit drives 5 V. Correction: the $R_{DS(on)}$ vs $V_{GS}$ curve at the actual drive voltage.
4. Threshold voltage treated as a turn-on voltage. $V_{GS(th)}$ is where 250 µA flows. A device with a 2 V threshold is not on at 3 V. Correction: full enhancement requires the gate voltage at which $R_{DS(on)}$ is specified.
5. Threshold spread ignored. Minimum threshold at high temperature can be less than half the typical at 25 °C. Correction: use the minimum, at temperature, for immunity calculations; the maximum for drive voltage sufficiency.
6. Switching times from the table. They belong to a specific test circuit with a specific gate resistor and resistive load. Correction: compute from gate charge and the actual drive current.
7. Capacitances at 25 V used at the operating voltage. $C_{OSS}$ at 25 V may be a third of its value at 5 V and three times its value at 100 V. Correction: $Q_G$, $Q_{GD}$, $Q_{oss}$, and $C_{O(er)}$ at the operating voltage.
8. $P_D$ and $R_{\theta JA}$ on the datasheet board. The stated $R_{\theta JA}$ assumes 1 in² of 2 oz copper or a test board defined by JEDEC. Correction: measure or estimate the actual board; the datasheet often provides $R_{\theta JA}$ vs copper area.
9. SOA at 25 °C case and single pulse. Correction: derate for case temperature, and for repetition.
10. DC SOA line taken as measured. On many trench parts it is calculated, and the device fails below it at high voltage. Correction: check the footnotes; prefer parts with measured linear-mode SOA for linear applications.
11. Body diode ignored in a synchronous rectifier. Reverse recovery loss appears in the opposite switch and rises with temperature. Correction: include $Q_{rr}$ at the operating temperature.
12. Avalanche rating used as a repetitive rating. $E_{AS}$ is single-pulse from 25 °C. Correction: repetitive avalanche needs the repetitive rating and a thermal calculation; better, clamp the spike.
13. Gate rating without ringing. ±20 V rating, 12 V drive, and 10 V of ringing on the gate. Correction: measure the gate at the pin; add damping.
14. Paralleled devices assumed to share. They share in the ohmic region through the positive temperature coefficient; they do not share switching transitions or linear operation. Correction: individual gate resistors, symmetric layout, source resistors in linear mode.
15. Transconductance at the wrong current. The datasheet $g_{fs}$ is at high current. At the low currents of a linear-mode ramp it is several times lower. Correction: the transfer characteristic graph at the operating current.
16. Junction temperature rating treated as an operating target. Failure rates roughly double per 10 °C. Correction: design to 110 to 125 °C.
17. $I_{DM}$ used without the SOA. The pulsed current rating is a wire-bond limit at short pulse widths. Correction: the SOA at the pulse width and voltage.
18. Leakage ignored at temperature. $I_{DSS}$ rises by orders of magnitude from 25 °C to 150 °C. Correction: check $I_{DSS}$ at temperature for high-impedance nodes, battery-powered off states, and series stacks.
19. Thermal instability discovered in the field. A hot-swap FET that passed bench tests at room temperature fails at high ambient. Correction: SOA verification at the worst-case case temperature, with margin.
20. Logic-level part chosen for 3.3 V drive. The 4.5 V specification is not a 3.3 V specification. Correction: a driver, or a device specified at 2.5 V or 3.3 V (increasingly available), checked at temperature.

Worked example 1: hard-switched buck converter

Requirement: 12 V input, 3.3 V output, 10 A, 500 kHz, synchronous buck. Duty cycle $D$ = 0.275. Inductor ripple 3 A peak-to-peak, so the high-side switch turns on at 8.5 A and off at 11.5 A. Gate drive 5 V from the controller, driver output resistance 1.5 Ω source and sink, 2.2 Ω external gate resistor. Ambient up to 60 °C.

High-side candidate. 30 V, logic-level, PowerPAK SO-8: $R_{DS(on)}$ 6 mΩ maximum at 4.5 V and 25 °C; normalized $R_{DS(on)}$ 1.5 at 100 °C; $Q_G$ 12 nC at 4.5 V; $Q_{GS}$ 4 nC; $Q_{GD}$ 3 nC; $V_{plateau}$ 3.0 V at 10 A; $V_{GS(th)}$ 1.2 V minimum; $R_{G(int)}$ 1 Ω; $C_{O(er)}$ 400 pF; $R_{\theta JA}$ 40 °C/W on 1 in² of 2 oz copper.

The junction temperature is consistent with the 1.5 $R_{DS(on)}$ multiplier assumed. Switching loss is twice the conduction loss, so a lower-$R_{DS(on)}$ device with higher charge would make the high side worse; a device with lower $Q_{GD}$ would improve it.

Low-side candidate. Same package, 2.5 mΩ maximum at 4.5 V, $Q_G$ 30 nC, $Q_{rr}$ 30 nC, body diode $V_F$ 0.8 V, $C_{RSS}$ 0.6 nF, dead time 20 ns each edge.

The low side is conduction-dominated, so its $R_{DS(on)}$ matters and its gate charge costs only driver power. The loss split justifies different devices in the two positions.

Induced turn-on check. The high side turns on with $dV/dt$ = 12 V / 7.0 ns = 1.7 V/ns. The low-side gate is held low through its internal 1 Ω plus the driver's 1.5 Ω pull-down. The induced gate voltage is approximately $0.6\ \text{nF} \times 1.7\ \text{V/ns} \times 2.5\ \Omega$ = 2.6 V, above the 1.2 V minimum threshold. This is a shoot-through risk. Options, in order of preference: a driver with a 0.5 Ω or lower pull-down (induced voltage about 1.5 Ω × 1.0 A = 1.5 V, still marginal), a driver with an integrated Miller clamp at the gate, a low-side device with a $Q_{GD}/Q_{GS}$ ratio below 1 and a higher threshold, or a larger high-side gate resistor to slow the edge, which raises high-side switching loss in proportion. The measurement to make on the bench is the low-side gate voltage at the pin during the high-side turn-on edge, at maximum input voltage and temperature.

Worked example 2: hot-swap pass FET

Requirement: 48 V nominal bus (36 to 60 V), 5 A load, 470 µF of load capacitance, controlled inrush, short-circuit protection, operating case temperature up to 70 °C. The controller drives the gate from a charge pump with a 20 µA source, senses current through a shunt, regulates the gate to hold the current limit during a fault for a timer period, and then latches off.

Figure 5. Hot-swap pass FET with the controller. The R-C on the gate sets the turn-on ramp; the resistor lets the controller's fast pull-down turn the device off in a fault without discharging the capacitor.

Voltage and gate. 100 V device: 60 V maximum bus times 1.5 is 90 V, and 48 V systems carry transients. The controller's gate drive reaches about 12 V above the source; the device's ±20 V gate rating is adequate, and the controller clamps the gate-source voltage internally.

Inrush by $dV/dt$ control. The 20 µA gate current into the 10 nF gate capacitor ramps the gate, and therefore the source (the device is a source follower during the ramp), at $dV/dt$ = 20 µA / 10 nF = 2 kV/s. The output reaches 48 V in 24 ms. The inrush current is $C_{LOAD} \, dV/dt$ = 470 µF × 2 kV/s = 0.94 A, below the current limit, so the ramp is set by the capacitor and the current limit does not engage. The 4.7 kΩ resistor drops 94 mV at 20 µA, which does not affect the ramp, and isolates the capacitor from the gate so the controller's fault pull-down (typically 1 to 2 A) turns the device off in microseconds.

Energy and power during the ramp. The device dissipates $\tfrac{1}{2} C V^2$ = 0.5 × 470 µF × 48² = 0.54 J, independent of ramp rate, as a triangular power pulse starting at 48 V × 0.94 A = 45 W and falling to zero over 24 ms. The load is held off by the controller's power-good output until the ramp completes; if it were enabled during the ramp, its current times the remaining drain-source voltage would add to the stress.

SOA check. The operating point is 48 V, 0.94 A, for a 24 ms pulse, at $T_C$ = 70 °C. A representative 100 V, 10 mΩ trench device in D2PAK has SOA lines at 48 V of about 2 A at 10 ms and 0.6 A at 100 ms; interpolating on the log-log plot gives about 1.2 A at 24 ms at $T_C$ = 25 °C. Derating for 70 °C with $T_{J,max}$ = 175 °C: factor 0.7, giving 0.84 A. The requirement of 0.94 A exceeds it. Two resolutions:

• Slow the ramp. A 22 nF gate capacitor gives 0.91 kV/s, a 53 ms ramp, and 0.43 A of inrush at a peak of 20 W. The 100 ms line at 48 V derated is 0.42 A, and the interpolated 53 ms value is about 0.56 A. Margin is 30 %, acceptable. Total energy is unchanged at 0.54 J; the longer pulse spreads it over more of the die's thermal mass.
• Select a linear-mode device. A device marketed for hot-swap use in the same package has a measured DC line at 48 V of 1.5 A or more, and the original 24 ms ramp is acceptable with margin.

A thermal-impedance calculation alone would not have caught the problem: 20 W average into a $Z_{\theta JC}$ of roughly 0.4 °C/W at 50 ms is a junction rise of under 10 °C. The SOA limit at 48 V is thermal instability, not average temperature.

Short-circuit event. The shunt is 5 mΩ with a 50 mV threshold, so the controller regulates the gate to hold 10 A into a short. The device sees 48 V × 10 A = 480 W until the fault timer expires. With a 1 ms timer, the SOA point is 48 V, 10 A, 1 ms. The representative device's 1 ms line at 48 V is about 15 A at 25 °C, 10.5 A derated to 70 °C: no margin. With a 300 µs timer, the interpolated line between 100 µs and 1 ms gives about 25 A, 17.5 A derated, a margin of 75 %. Set the timer to 300 µs, or reduce the current limit to 7 A. The energy per event is 0.14 J at 300 µs, and repeated retries must be spaced by the thermal time constant; auto-retry at a low duty cycle or latch-off.

Steady state. 5 A through 10 mΩ hot (about 16 mΩ at the operating temperature) dissipates 0.4 W, a 16 °C rise at 40 °C/W. $R_{DS(on)}$ does not drive the selection; the SOA does.

Selection summary. 100 V, D2PAK or larger, linear-mode SOA verified at 48 V for the ramp duration and the fault timer at the maximum case temperature with margin, gate rating above the controller's drive, and $R_{DS(on)}$ as a secondary criterion for steady-state loss. The lowest-$R_{DS(on)}$ part in the voltage class is the worst candidate for this position.

Limitations of this document

• Loss equations use the piecewise-linear switching model. They are adequate for selection and thermal budgeting to within about 30 %; final values come from simulation with the manufacturer's model or from measurement.
• SOA figures for the "representative device" in the hot-swap example are illustrative of the class. Every design must use the actual device's SOA graph and footnotes.
• Temperature coefficients, capacitance ratios, and normalized curves vary between processes. The ranges quoted are typical of silicon power MOSFETs; SiC and GaN devices differ in threshold behavior, gate ratings, body diode characteristics, and $C_{OSS}$ non-linearity.
• Thermal resistance on a real board depends on copper area, layer count, vias, airflow, and neighboring components. Values used here are placeholders for that calculation.