SMPS Crash Course

The energy picture

A linear regulator drops the unwanted voltage across a transistor and turns the product of that drop and the load current into heat. A switching converter avoids the drop entirely: the transistor is either fully on (no voltage across it) or fully off (no current through it), and an inductor and a capacitor turn the resulting pulses into a smooth output. The only losses are the switching transitions and the parasitic resistances, which is why 90 to 98 % efficiency is normal.

The inductor is the element that makes this work. It resists changes in current: with voltage $V$ across it, its current changes at $dI/dt = V/L$, and the energy it holds is $\tfrac{1}{2} L I^2$. In every PWM converter the cycle has two intervals. During one, the inductor is connected so that current rises and energy flows into it from the input. During the other, it is connected so that current falls and the stored energy flows out toward the output. The capacitor at the output absorbs the pulsating current and holds the voltage steady between pulses.

How a buck lowers the voltage. The switch chops the input into a rectangular wave that is $V_{IN}$ for a fraction $D$ of each period and zero for the rest. The average of that wave is $D \cdot V_{IN}$. The inductor and capacitor form a low-pass filter whose corner is far below the switching frequency, so the output is the average: a lower voltage, with the inductor carrying the full load current continuously. Current is delivered to the output during the whole cycle; the input supplies it only during the on-time, at a higher current than the output receives on average, so input power equals output power.

How a boost raises the voltage. During the on-time the switch shorts the inductor across the input, and current ramps up with the output disconnected; the load runs from the output capacitor. When the switch opens, the inductor's current cannot stop, so its voltage reverses and rises to whatever is needed to keep the current flowing, which means the inductor voltage stacks on top of the input and forward-biases the diode into the output. The output is above the input because the inductor adds its voltage in series with the source during the off-time. Energy reaches the output only during the off-time, which is why boost converters have discontinuous output current and larger output ripple, and why their control has a right-half-plane zero.

Volt-second balance is the rule that gives every conversion ratio. In steady state the inductor current ends each cycle where it started, so the average inductor voltage over a cycle is zero: the volt-seconds applied during the on-time equal the volt-seconds removed during the off-time.

For a buck, $V_{on} = V_{IN} - V_{OUT}$ and $V_{off} = V_{OUT}$, which gives $V_{OUT} = D\, V_{IN}$. For a boost, $V_{on} = V_{IN}$ and $V_{off} = V_{OUT} - V_{IN}$, which gives $V_{OUT} = V_{IN} / (1 - D)$. The companion rule, charge balance, states that the average capacitor current over a cycle is zero, and it gives the average currents. These two rules, applied to each interval, derive any PWM converter.

Topologies

Figure 1. Buck converter. The switch and diode (or synchronous MOSFET) apply either the input or zero to the inductor; the LC filter passes the average.

Figure 2. Boost converter. The inductor is charged from the input with the switch closed and discharges into the output, in series with the input, when the switch opens.

$n$ is the secondary-to-primary turns ratio. The ratios hold for continuous conduction and ideal components.

Continuous and discontinuous conduction

Figure 3. Inductor current in continuous conduction (top) and discontinuous conduction (bottom). In DCM the current reaches zero before the cycle ends and the switch node rings while it idles.

In continuous conduction mode (CCM) the inductor current never reaches zero. It ramps between a valley and a peak around the average, the conversion ratio depends only on duty cycle, and the ripple is

In discontinuous conduction mode (DCM) the load current is small enough that the inductor current falls to zero during the off-time and stays there until the next cycle. The boundary occurs when the average current equals half the ripple: $I_{OUT} = \Delta I_L / 2$. Consequences:

• The conversion ratio depends on load as well as duty cycle: at light load, a given duty cycle produces a higher output, so the controller must reduce $D$ as the load drops.
• The power stage becomes first-order (the inductor is not a state that carries over between cycles), which makes the control loop easier, and the right-half-plane zero of boost and buck-boost moves to high frequency.
• Peak currents are higher for the same average, so conduction loss and core loss rise relative to CCM at the same power.
• The switch node rings at the resonance of the inductor with the switch and diode capacitance when the current reaches zero. It is harmless but appears on the scope and radiates.
• A diode-rectified converter enters DCM at light load; a synchronous converter stays in CCM with negative inductor current unless the controller turns the synchronous switch off at zero current, which most do at light load to save the circulating loss.

The design choice is the inductance. A larger inductor keeps the converter in CCM to lighter loads, lowers ripple and peak current, and slows the transient response; a smaller inductor does the reverse. The usual starting point is a ripple of 20 to 40 % of the rated output current at nominal input.

Ripple and stress equations for a buck in CCM, needed for component selection:

Isolated converters

Isolation is required when the output must float relative to the input for safety (mains-connected supplies), for ground-loop breaking, or to reach a ratio that a non-isolated stage cannot. The transformer also provides the ratio $n$ and, in the flyback, the energy storage.

Figure 4. Flyback converter. The transformer is a coupled inductor with a gapped core: energy is stored during the on-time and released to the secondary during the off-time.

Flyback. The "transformer" is an inductor with two windings. While the switch is on, the primary stores energy in the gap and the secondary diode is reverse-biased. When the switch opens, the secondary delivers that energy. It is the boost converter with the inductor split into two windings, and it inherits the boost's right-half-plane zero in CCM and its pulsating output current. Its economy (one switch, one magnetic component, one diode per output, easy multiple outputs) makes it the standard below about 100 W. The leakage inductance of the primary is not coupled to the secondary and has nowhere to put its energy when the switch opens, so a clamp (RCD, Zener, or an active clamp) across the primary is mandatory, and it dissipates that energy every cycle.

Forward, push-pull, half-bridge, full-bridge. These use a true transformer that transfers energy during the on-time, with a separate output inductor. The transformer stores no energy, so its core is not gapped and can be smaller, but its magnetizing flux must return to zero every cycle. The single-switch forward uses a reset winding or an active clamp; the bridge topologies alternate polarity so the flux balances by symmetry, and push-pull and full-bridge require current-mode control or a series capacitor to prevent a flux walk from saturating the core.

Feedback across the barrier. The error amplifier is usually on the secondary (a TL431 with the divider) driving an optocoupler whose transistor sits on the primary side at the controller. The optocoupler's current transfer ratio varies 2:1 between parts, degrades with age, and rolls off at 5 to 50 kHz, and all of that is inside the loop. Primary-side regulation (sensing a bias winding) removes the optocoupler at the cost of load regulation. Digital isolators with a secondary-side controller remove it at the cost of a controller.

Safety spacing. Creepage and clearance across the barrier are dimensioned by IEC 60664-1 and the product standard; the creepage and clearance calculator on the tools page covers it. The transformer's insulation system and the optocoupler's rating must match.

Control methods

The controller adjusts the duty cycle (or frequency) so that the output follows a reference. The modulator is the block that turns the control voltage into switch timing, and its type determines the dynamics of the power stage as the loop sees them.

Voltage mode. The error amplifier output $V_C$ is compared against a fixed sawtooth ramp; the switch is on while the ramp is below $V_C$. Duty cycle is proportional to $V_C$. The loop sees the LC filter as a second-order system with a resonant double pole at $f_0 = 1/(2\pi\sqrt{LC})$ and a Q set by the load and the parasitic resistances, followed by the ESR zero of the output capacitor. The double pole contributes a 180° phase lag over a narrow band, which makes the compensation demanding (Type III). Input voltage changes appear as gain changes unless the ramp amplitude is scaled with the input (voltage feedforward). Voltage mode is preferred where the sensed current is noisy or the duty cycle is very small.

Peak current mode. The error amplifier output sets a current threshold. Each cycle, a clock turns the switch on, the inductor current ramps up, and a comparator turns the switch off when the sensed current reaches the threshold.

Figure 5. Peak current-mode modulator. The outer voltage loop sets the current threshold; the inner comparator loop ends each cycle when the sensed inductor current, plus the compensation ramp, reaches it.

The inner loop makes the inductor look like a current source commanded by $V_C$, which removes the inductor from the outer loop's dynamics. The power stage becomes first-order: a single pole set by the output capacitor and the load, $f_p = 1/(2\pi R_{LOAD} C_{OUT})$, plus the ESR zero, plus a pair of poles at half the switching frequency from the sampling nature of the comparator. Compensation is simpler (Type II), the loop can be faster, input voltage changes are rejected within a cycle because the current threshold does not depend on $V_{IN}$, cycle-by-cycle current limiting is inherent, and paralleled converters share current. The costs are the sense element and its noise, a minimum on-time needed for the leading-edge blanking of the sense signal, and the subharmonic instability described next.

Slope compensation. In peak current mode with the duty cycle above 50 %, a small disturbance in the inductor current grows from cycle to cycle rather than decaying:

Figure 6. Subharmonic oscillation. Without slope compensation (top), a perturbation in the valley current grows by the ratio of the down-slope to the up-slope each cycle when the duty cycle exceeds 0.5. Adding a ramp of slope at least half the down-slope to the sensed current (bottom) makes it decay.

The mechanism is geometric. The switch turns off when the up-slope $m_1$ reaches the threshold; a perturbation $\Delta I$ in the starting current shortens the on-time by $\Delta I / m_1$, which lengthens the off-time by the same amount, during which the current falls at $m_2$, so the next starting current is off by $\Delta I \cdot m_2 / m_1$. For $D > 0.5$, $m_2 > m_1$ and the error grows, alternating sign: the converter runs at half the switching frequency with alternating wide and narrow pulses. The fix is to subtract a ramp of slope $m_a$ from the threshold (equivalently, add it to the sensed current), which changes the per-cycle error ratio to $(m_2 - m_a)/(m_1 + m_a)$. With $m_a \geq m_2 / 2$ the ratio is below one at any duty cycle; with $m_a = m_2$ the error is removed in one cycle, which is the usual design target. Most integrated controllers add a fixed ramp internally sized for their intended inductor range, and the datasheet gives the minimum inductance at which it is sufficient. The ramp also reduces the effective peak current limit at high duty cycle, because the threshold is lower by $m_a \cdot D T$ at the end of the on-time.

Other modulators. Average current mode senses and filters the inductor current and closes a true current loop; it is used in PFC and where the peak-sensing noise problem is severe. Valley current mode and emulated current mode suit very short on-times. Constant on-time and hysteretic (ripple-based) control have no clock and no error amplifier in the classic sense, respond within one cycle, and rely on the output ripple as the ramp, which makes them sensitive to the output capacitor's ESR and to capacitor changes; they dominate in point-of-load regulators for processors. Frequency modulation regulates resonant converters.

Control theory for the loop

Figure 7. The regulation loop. The compensator, modulator, power stage, and feedback divider form the loop gain; the loop rejects disturbances entering at the power stage by the factor 1 + T.

The loop gain $T(s)$ is the product of everything around the loop: the compensator $G_c(s)$, the modulator gain $F_m$, the power stage transfer function from control input to output $G_p(s)$, and the divider $H$. It determines everything about regulation:

• The output error in response to a disturbance (line, load) is the open-loop error divided by $|1 + T|$. Where $|T| \gg 1$, the loop regulates; where $|T| \ll 1$, it does not.
• The crossover frequency $f_c$ is where $|T| = 1$ (0 dB). Above it the loop has no authority; the output capacitor alone handles transients. Load-step deviation is inversely proportional to $f_c$, which is why a fast loop allows a smaller output capacitor.
• The phase margin is $180° + \angle T(f_c)$. It is the distance from the condition $T = -1$, at which the loop is an oscillator. Below about 30° the transient response rings for many cycles; 45° gives a well-damped response with some overshoot; 60° or more gives no overshoot at the cost of a slower settle. Design to 45° to 60° across all line and load conditions and temperatures, because component tolerance and the ceramic capacitor's voltage coefficient move the phase.
• The gain margin is how far $|T|$ is below 0 dB at the frequency where the phase reaches -180°. It protects against gain increases (from tolerance, ESR changes, or the input voltage in a voltage-mode converter). 10 dB is a normal target.
• The slope of $|T|$ through crossover should be -20 dB/decade. A -40 dB/decade slope at crossover means the phase there is near -180° and the margin is poor.

Figure 8. Loop gain and phase. Crossover is where the gain crosses 0 dB; phase margin is measured there. Gain margin is measured where the phase reaches -180°.

Power stage transfer functions, which the compensator must be designed against:

The right-half-plane zero deserves its own sentence. When a boost converter is asked for more output, the controller lengthens the on-time, which shortens the off-time, which is the only interval in which energy reaches the output. The output first falls, then rises as the inductor current builds. A response that goes the wrong way first is a right-half-plane zero, and no compensator removes it; the loop must be slower than it. Its frequency is lowest at low input voltage and full load, so that is where it is checked.

Crossover targets. $f_{sw}/10$ to $f_{sw}/5$ for voltage mode, up to $f_{sw}/6$ for current mode, below $f_{RHPZ}/4$ where one exists, and below the optocoupler pole. The switching frequency itself is set by the trade between inductor and capacitor size (higher is smaller), switching loss (higher is worse), and the achievable loop bandwidth.

Compensation networks

The compensator shapes $T(s)$ so that it crosses 0 dB at the target frequency with the target phase margin, and has high gain at low frequency for regulation accuracy. Every compensator has an integrator (a pole at the origin) for zero DC error, and adds zeros and poles to cancel or work around the power stage's features.

Type II. One zero and one high-frequency pole, plus the origin pole. It provides up to about 90° of phase boost between the zero and the pole. It is the standard for current-mode converters, whose single-pole power stage needs only one zero to cancel the lag, and for DCM converters.

Figure 9. Type II compensator. The zero at 1/(2π R3 C1) restores phase around crossover; the pole at 1/(2π R3 C2) rolls off switching noise; R3/R1 sets the mid-band gain.

Placement for a current-mode buck: the zero at about one fifth of the crossover frequency (so its phase boost is largely in by $f_c$), the pole at the ESR zero of the output capacitor or at $f_{sw}/2$, whichever is lower, and the mid-band gain set so that $|T(f_c)| = 1$.

Type III. Two zeros and two high-frequency poles, plus the origin pole. It provides up to about 180° of phase boost, needed to counter the LC double pole of a voltage-mode converter.

Figure 10. Type III compensator. The added network R4 and C3 across R1 contributes a second zero and a second pole, giving the phase boost needed to cross over above an LC double pole.

Placement for a voltage-mode buck: both zeros at or slightly below the LC resonance $f_0$ (one at $0.5 f_0$, one at $f_0$ is common), one pole at the ESR zero to cancel it, and the other at $f_{sw}/2$. Crossover is then set above $f_0$ by the mid-band gain. If the ESR zero is above $f_{sw}/2$ (ceramic capacitors), both poles go to $f_{sw}/2$.

Transconductance amplifier compensation. Most integrated controllers do not expose an op-amp with a feedback pin. The error amplifier is a transconductance stage whose output current flows into a network from the COMP pin to ground, and the network is a Type II by construction.

Figure 11. Compensation on a transconductance error amplifier, the form found on most controller ICs. The series R and C set the zero and mid-band gain; the small parallel C sets the high-frequency pole.

The mid-band gain is $g_m R_c$ times the divider ratio, the zero is at $1/(2\pi R_c C_c)$, and the high-frequency pole is at $1/(2\pi R_c C_p)$. Because the gain depends on the divider ratio $V_{REF}/V_{OUT}$, a higher output voltage lowers the loop gain for the same network; the datasheet's compensation values are for its stated output voltage. A capacitor across the upper divider resistor (feedforward capacitor) adds a zero-pole pair that can be used for extra phase boost, and many datasheets specify one.

What each element does, in words. The origin pole (the integrator) gives infinite DC gain so the output settles exactly on the reference. The zero stops the integrator's -90° from combining with the power stage's lag into -180° at crossover; it turns the compensator from an integrator into a flat gain at the frequencies where the loop crosses over. The high-frequency pole restores the roll-off above crossover so that switching ripple on the feedback does not reach the modulator with enough amplitude to jitter the duty cycle. The mid-band gain is the knob that positions crossover: raise it and $f_c$ rises until the phase margin runs out or the $f_{sw}/2$ poles or the RHP zero are reached.

Traps in controller ICs and reference designs

1. The reference design's output capacitor is part of the compensation. Its capacitance and ESR set the power-stage pole and zero that the compensation was designed against. Substituting a ceramic for an electrolytic removes the ESR zero the Type II pole was placed on; substituting a different capacitance moves the pole. Recompensate whenever the output capacitor changes.
2. Ceramic capacitor DC bias. A 22 µF, 6.3 V, 0805 X5R capacitor can be 6 to 8 µF at 5 V. Every ripple, transient, and loop calculation must use the effective capacitance at the operating voltage, from the manufacturer's curve, not the marked value.
3. Minimum on-time. Current-mode controllers blank the sense comparator for 50 to 150 ns after turn-on. At high switching frequency and high step-down ratio, the required on-time $D / f_{sw}$ falls below it, and the converter skips pulses, raising output ripple and losing regulation. Check $V_{OUT} / (V_{IN,max} f_{sw})$ against the datasheet minimum.
4. Maximum duty cycle and the bootstrap capacitor. A high-side N-channel driver needs the switch node to fall each cycle to recharge the bootstrap capacitor, which limits the maximum duty cycle and therefore the minimum input voltage for a given output. At dropout the converter may skip cycles or lose gate drive.
5. Internal slope compensation assumes an inductor range. The internal ramp is fixed; an inductor below the datasheet minimum leaves the ramp insufficient at high duty cycle and the converter runs subharmonic. Datasheets state the condition, usually as a minimum inductance versus output voltage.
6. Current limit is not output current. A peak current limit trips at the inductor peak, which is the average plus half the ripple, and is reduced by slope compensation at high duty cycle. A valley limit trips at the average minus half the ripple. The datasheet number is the comparator threshold; the achievable output current is derived from it and the ripple.
7. Inductor saturation is soft and thermal. Ferrite saturates sharply and the current spikes within the cycle; powdered-iron rolls off gradually. Both derate with temperature. The peak current, including the load-step overshoot before the loop responds and the current-limit level, must stay below the saturation current at the hot inductor.
8. Light-load modes change the behavior. Pulse-skipping and burst modes improve light-load efficiency and produce output ripple at an audible or otherwise variable frequency, larger than in PWM mode. The mode transition can interact with the loop. Noise-sensitive loads may need forced PWM.
9. Layout is part of the design. The hot loop (input capacitor, high-side switch, low-side switch or diode) must be as small as the parts allow, with the input capacitor closest to the switches; the gate drive loop must be short; the feedback trace must run away from the switch node and the inductor; the current sense must be a Kelvin connection to the sense resistor pads. A reference design's layout is part of its compensation, because the loop's parasitics are in it.
10. Feedback divider impedance. A high-impedance divider picks up the switch node capacitively and adds a pole with the feedback pin's input capacitance. Keep the lower resistor in the 1 to 20 kΩ range unless quiescent current forces otherwise, and route the divider at the feedback pin.
11. Thermal figures are for the evaluation board. The datasheet's $R_{\theta JA}$ assumes a four-layer board with a large copper area. A two-layer board with minimal copper can double it. Compute the junction temperature from the loss and the real board.
12. Efficiency curves are for the evaluation board's inductor. Inductor DCR and core loss are a large fraction of the loss at both ends of the load range; a cheaper inductor gives a lower curve.
13. Pre-biased outputs. A synchronous converter starting into an output that is already held up by another supply will sink current through the low-side switch and discharge it unless the controller supports pre-bias start-up.
14. Input filter interaction. An input LC filter (EMI filter, long leads with a ceramic input capacitor) has an output impedance peak at its resonance. A regulating converter presents a negative incremental input resistance. If the filter's peak impedance exceeds the converter's input resistance magnitude, the combination oscillates. Damping (an electrolytic capacitor with ESR across the ceramic) is the fix.
15. Hot-plug into a ceramic input. Connecting a live source through inductive leads to a ceramic input capacitor produces a voltage overshoot of up to twice the source voltage at the input pin. Add a damped electrolytic or a TVS, or derate the input rating.
16. The evaluation board was tested at one condition. Stability and regulation are verified at the corners of line, load, and temperature, and with the actual inductor and capacitors of the production design.
17. Sense resistor parasitics. The inductance of the sense resistor and its traces produces a leading-edge spike in the sensed current; the filter that removes it also delays the sense signal and lowers the current limit. Use the datasheet's recommended filter values and a low-inductance resistor.
18. Soft-start and inrush. Without a controlled soft-start, the loop saturates at start-up and the inductor current reaches the current limit while charging the output capacitor, and can trip the input supply. Set the soft-start time from the output capacitance and the current available.
19. Dead time and body diode. In synchronous converters the body diode conducts during dead time and adds loss and reverse recovery. Controllers with adaptive dead time handle it; fixed dead time must exceed the gate drive delays at the worst-case gate charge.
20. Feedback pin at start-up and in fault. The reference and the error amplifier are not valid until the controller's bias is up; the compensation capacitor must be discharged for a clean restart; and after a fault the hiccup timing determines the average short-circuit current.

Testing a converter

Measurements, in the order they find problems:

Start-up. Output rise with a scope on input current, output voltage, and the switch node: monotonic rise, no overshoot, inrush within the source's capability, soft-start time as designed. Repeat at maximum load, minimum load, and into a pre-biased output if applicable.

Line regulation. Output voltage across the input range at a fixed load, reported as the peak deviation in percent or millivolts. A current-mode converter shows almost none; a voltage-mode converter without feedforward shows some. The measurement must be made with the output sensed at the load point through separate wires.

Load regulation. Output voltage across the load range at a fixed input. Deviation comes from the error amplifier's finite DC gain, from IR drops between the sense point and the load, and, in hysteretic converters, from the ripple-based control law. Again, Kelvin-sense at the load.

Efficiency. Input and output power at each load point, with voltages sensed at the converter's terminals and currents measured with shunts or meters in series, not from the supply's display. Plot across load; the light-load region shows the fixed losses and the heavy-load region the conduction losses.

Output ripple and noise. The probe ground lead is the usual error: a 15 cm ground clip picks up the switching magnetic field and shows ripple that is not there. Use a probe with a short ground spring at the output capacitor, a 20 MHz bandwidth limit for the ripple figure and full bandwidth for the switching spikes, and state which was used.

Load transient. Step the load from 25 % to 75 % and back with an edge fast compared with the loop (an electronic load in dynamic mode, or a MOSFET and resistor switched by a pulse generator), and record the output. The deviation gives the effective output impedance at the loop's bandwidth; the ring frequency is close to the crossover frequency; the number of ring cycles indicates the phase margin, with about 20 % overshoot and one overshoot corresponding to 45° and a critically damped response to 60° or more. This is the test that reveals a marginal loop without a network analyzer.

Loop gain measurement. The direct measurement of $T(s)$: inject a small signal into the loop through a resistor in the feedback path and measure the ratio of the voltages on the two sides of it.

Figure 12. Loop gain measurement by injection. A small resistor in the feedback path carries the injected signal; the loop gain is the ratio of the signals on the output side and the divider side of it.

The injection point must be where the loop is broken by a low impedance looking back and a high impedance looking forward, which the output node feeding a resistive divider satisfies. The injection amplitude is kept small enough that the loop stays linear (10 to 50 mV at the output, reduced near crossover), the sweep runs from below the compensator zero to half the switching frequency, and the result is read directly for crossover, phase margin, and gain margin. Measure at minimum and maximum input, minimum and maximum load, and cold and hot; the worst case is usually at maximum input and minimum load for a buck (highest gain, DCM boundary) and at minimum input and maximum load for a boost (lowest RHP zero).

Current limit and short circuit. Ramp the load until the limit engages; then apply a dead short and confirm the converter survives indefinitely, the average current in hiccup is acceptable, and it recovers when the short is removed.

Thermal. At maximum load and input in the enclosure, with the inductor, switches, and diode temperatures measured by thermocouple or thermal camera, against the derated ratings.

EMI. Conducted emissions with a LISN and radiated emissions in a chamber, at pre-compliance level during development. Most failures trace to the hot loop area, the switch node area, and the input filter's damping.

Design procedure

1. Specification: input range, output voltage and current range, ripple, transient limits, efficiency, isolation, ambient temperature, size.
2. Topology from the ratio, isolation, and power level.
3. Switching frequency from the size, efficiency, and bandwidth trade.
4. Inductor from the ripple target at nominal input; check peak current against saturation, and the DCM boundary against the minimum load.
5. Output capacitor from the ripple and the load-step deviation at the intended crossover; use effective capacitance at the DC bias.
6. Input capacitor from the RMS current and the input ripple.
7. Switches and diode from the voltage stress with margin, the RMS currents, and the loss estimate; gate drive from the controller's capability.
8. Controller: control method, current sense, minimum on-time, maximum duty, slope compensation range, protection features.
9. Compensation: identify the power stage's poles and zeros at the worst-case corner, choose the crossover, place the compensator's zeros and poles, set the mid-band gain, and check the phase margin at all corners.
10. Layout with the hot loop, gate loop, and feedback path as constraints.
11. Test in the order above.

Worked example: current-mode buck compensation

Requirement: 12 V input (8 to 16 V), 3.3 V output, 3 A, 500 kHz, peak current-mode controller with a transconductance error amplifier of $g_m$ = 1 mS, reference 0.8 V, current-sense gain 3 A per volt of control voltage. Output capacitors two 22 µF ceramics with about 30 µF effective at 3.3 V and 5 mΩ combined ESR.

Phase at crossover: -90° from the origin pole, -84.5° from the power-stage pole at 4.8 kHz, +78.7° from the zero at 10 kHz, -11.3° from the pole at 250 kHz, and about -19° from the sampling double pole at 250 kHz with the controller's slope compensation. The sum is -126°, a phase margin of 54°. A 1.5 A load step produces a deviation of about $1.5 / (2\pi \times 50\ \text{kHz} \times 30\ \mu\text{F})$ = 160 mV, which the output capacitor value can be raised to reduce if required.

At 8 V input the duty cycle is 0.41; at the 5 V input some controllers allow, it would be 0.66 and the internal slope compensation must cover it. At minimum load the converter enters DCM below 0.51 A unless forced-PWM is enabled, and the power-stage pole moves with the load: at 0.3 A the pole is at 0.48 kHz and the crossover drops to about 5 kHz with the phase margin increasing, which is acceptable. The loop is then measured by injection at 8 V and 16 V input, at 0.3 A and 3 A, and the transient response checked at each.

Limitations of this document

• Transfer functions are the standard small-signal averaged models; they neglect the modulator's sampling effects except where stated and are valid below about one third of the switching frequency.
• Component values in the worked example are illustrative; the controller's datasheet defines its transconductance, sense gain, slope compensation, and minimum timing, and those numbers replace the ones assumed here.
• Resonant converters, power factor correction, and digital control have their own methods and are only named here.
• Efficiency, thermal, and EMI results depend on the layout and the specific parts and must be measured; nothing in this document substitutes for the tests in the testing section.