PCB Layout Best Practices

The signal is the field

Figure 2. A microstrip in cross section. The energy of the signal is in the fields between the trace and the plane, and the return current in the plane concentrates beneath the trace.

A signal on a trace is not a current in a wire. It is an electromagnetic field in the dielectric between the trace and its return conductor, propagating at the speed of light in that dielectric, with a current on the trace and an equal and opposite current on the return as the boundary conditions of that field. The trace is one half of the transmission line and the plane is the other half. Every layout rule follows from three consequences of this picture.

The first is that the return current is not "in the ground". It is directly beneath the trace, and it spreads only about three trace heights either side. At DC and audio frequencies the return spreads across the plane to minimize resistance. Above a few hundred kilohertz the return follows the path of least inductance, which is the path that keeps the loop between signal and return smallest, and that path is directly under the trace. Bogatin's demonstration board, Hartley's return-current lectures, and every field solver show the same picture: the current density in the plane under a trace falls off as $1 / (1 + (d/h)^2)$, with $d$ the distance from the trace centerline and $h$ the height above the plane, so 80 % of the return lies within three heights of the trace.

The second is that anything that disturbs the space between the trace and the plane disturbs the signal. A slot in the plane, a layer change to a different reference, a plane edge, a gap between two planes, a region of missing copper under a connector: each forces the return current to detour, and the detour is inductance in series with the signal, a discontinuity that reflects part of the edge, and a loop that radiates and couples.

The third is that the loop area between the signal and its return sets the inductance, and inductance sets almost every high-frequency problem: ground bounce, crosstalk, radiated emissions, susceptibility, and the impedance of the power distribution.

Loop inductance

Figure 3. The loop between a trace and its return plane is the trace length times the height above the plane. Halving the height halves the inductance.

For a trace of width $w$ at height $h$ above a plane, with $w$ larger than $h$, the loop inductance per length is approximately

$$L' \approx \mu_0 \frac{h}{w} \approx 32\ \text{nH/in} \cdot \frac{h}{w}$$

A 10 mil trace 4 mil above the plane has about 13 nH per inch; the same trace 20 mil above the plane has about 64 nH per inch. The formula is approximate for narrow traces, where fringing fields add a logarithmic term, but the scaling is what matters: inductance is proportional to the height above the reference and inversely proportional to the width. The same rule applies to a power trace, a decoupling capacitor's loop, and a via. It is the reason thin dielectrics between signal layers and their planes are the single most valuable feature of a stackup.

The voltage developed across that inductance is $L\,di/dt$. A 1 nH loop carrying an edge of 1 A per nanosecond drops 1 V. A 100 mA logic edge in 1 ns across 5 nH of ground path is 0.5 V of ground bounce. These are the numbers that make a 3.3 V logic family fail its noise margin.

Bandwidth of an edge

Figure 4. Spectrum envelope of a 10 MHz clock with 1 ns edges. The clock rate sets the first corner; the edge rate sets the content that matters for layout.

The bandwidth of a digital signal is set by its edge, not its clock. A trapezoidal edge of rise time $t_r$ has a spectrum that is flat up to $1 / (\pi \cdot \text{pulse width})$, falls at 20 dB per decade to $1 / (\pi t_r)$, and 40 dB per decade beyond. The useful bandwidth, the highest frequency with significant energy, is

$$f_{knee} \approx \frac{0.35}{t_r} \quad \text{(Bogatin)} \qquad f_{knee} \approx \frac{0.5}{t_r} \quad \text{(Johnson, more conservative)}$$

A 1 ns edge has content to 350 to 500 MHz regardless of whether it toggles at 1 kHz or 100 MHz. A modern microcontroller GPIO has an edge of 1 to 2 ns; an FPGA output has 200 to 500 ps; a low-speed I2C line has 50 ns. The edge rate is what determines whether a net is a transmission line, how much it couples into its neighbors, and how much it radiates.

The rule for when a trace must be treated as a transmission line: when the round-trip delay of the trace is comparable to or longer than the edge. On FR-4 a signal travels about 6 inches per nanosecond, so the critical length is

$$\ell_{crit} \approx \frac{t_r \cdot v}{2} \approx 3\ \text{in} \cdot \frac{t_r}{1\ \text{ns}}$$

Beyond that length an unterminated trace rings. For a 1 ns edge, 3 inches; for a 200 ps edge, 0.6 inches. Traces shorter than about one sixth of that behave as lumped elements and can be routed without regard to impedance. Between the two, termination is a judgment call informed by the receiver's tolerance to overshoot.

Transmission lines

Figure 5. Microstrip and stripline in cross section with the closed-form impedance and delay expressions from IPC-2141.

A trace over a plane is a transmission line with a characteristic impedance set entirely by geometry and dielectric constant: $Z_0 = \sqrt{L' / C'}$, where $L'$ and $C'$ are the inductance and capacitance per length. Narrower trace or thicker dielectric raises $Z_0$; wider trace or thinner dielectric lowers it. The closed forms in Figure 5 are from IPC-2141 and are good to about 5 % within their stated range; the number on the fabrication drawing comes from a field solver, either the fabricator's or a tool such as the Saturn PCB toolkit or Polar Si9000.

For 50 Ω on FR-4, a microstrip is about twice as wide as its dielectric height; a stripline is about as wide as its height to the nearer plane. A 4 mil dielectric gives a 7 to 8 mil microstrip; a 3 mil dielectric gives about 5 mil. This is why thin dielectrics and narrow traces go together, and why a 62 mil two-layer board cannot have a 50 Ω trace of sensible width: it would need to be 110 mil wide.

Losses matter above about 1 GHz or over long runs. Conductor loss rises with $\sqrt{f}$ through skin effect and with copper roughness; dielectric loss rises with $f$ through the loss tangent $\tan\delta$. Standard FR-4 has $\tan\delta$ around 0.02; low-loss laminates have 0.002 to 0.005. At 5 Gb/s over 10 inches the difference is several decibels of eye closure.

Propagation delay and timing

Figure 6. Propagation delay per inch for stripline and microstrip against dielectric constant. On FR-4 the two differ by about 20 %, which matters for any length match.

Signals travel at $c / \sqrt{\varepsilon_{eff}}$. For stripline $\varepsilon_{eff} = \varepsilon_r$ and the delay on FR-4 is about 174 ps/in, or 6.9 mm per 50 ps. For microstrip, with half the field in air, $\varepsilon_{eff} \approx 0.475\,\varepsilon_r + 0.67$ and the delay is about 140 ps/in. The 20 % difference means a length match done in millimeters is wrong if the matched signals are on different layer types. Match in delay, and where a matched group must change layers, change them all the same way.

The timing budget for a source-synchronous bus, DDR memory for instance, is the sum of the clock-to-data skew the receiver tolerates, the driver's own skew, the crosstalk-induced jitter, and the routing mismatch. A typical DDR3 budget allows about 20 ps of routing mismatch within a byte lane, which is about 3 mm of stripline. Serpentine tuning to hit that number has its own rules: keep the serpentine segments at least 3 to 4 heights apart so the signal does not couple across them and arrive early, keep serpentines away from other signals, and put the tuning near the end of the route where the trace already has the mismatch. Match the whole path: package length, via depth, and connector pins count.

Dielectric constant is not one number. It varies with frequency, with the glass-to-resin ratio of the prepreg, and locally with the glass weave, so that a trace running over a glass bundle and its pair partner running over a resin window see different velocities. For a high-speed differential pair over a long run, the fiber-weave effect can add tens of picoseconds of skew. The mitigations are a spread-glass laminate, a route angled 10° to the weave, or a zig-zag route. For most boards below a few gigabits per second it does not matter; for a 10 Gb/s SerDes over 20 inches it does.

What drives the decision

The four-layer question

The classic four-layer build, signal / ground / power / signal, puts the two planes about 40 mil apart on a 62 mil board. That spacing gives almost no plane capacitance, so the power plane contributes nothing to decoupling above a few megahertz, and the bottom signal layer references the power plane, which means every bottom-layer return current has to find a capacitor to get to ground. Hartley's recommendation, which Ritchey and Peterson share, is signal / ground / ground / signal for a four-layer board carrying anything fast: both signal layers get a ground reference, the two ground planes are stitched together by vias everywhere, and power is routed as wide traces and small pours on the outer layers, decoupled locally. The 40 mil of core between the two ground planes then carries nothing that matters.

On a six-layer board the classic choice is signal / ground / signal / power / ground / signal, which gives every signal layer a ground reference except L3, which references L2 from above, and puts the power plane against a ground plane. An eight-layer build has enough planes to pair every signal layer with a ground and still keep a power-ground pair.

Materials

Standard FR-4 (Dk about 4.2 to 4.6 at 1 GHz, tan δ about 0.02) is adequate to about 3 Gb/s or 2 GHz. Mid-loss laminates (Isola 370HR, FR408HR, Panasonic Megtron 4) extend that to 10 Gb/s. Low-loss (Megtron 6, Rogers 4350B, Tachyon) are for 25 Gb/s and above, or for RF where the phase must be stable. Rogers 4003C and 4350B are the usual choice for an RF layer pair because they process like FR-4. PTFE laminates do not, and cost accordingly. Specify the material by name and glass style on the fab drawing, not "FR-4", when impedance or loss is controlled; "FR-4" is a flammability rating, not a material.

One unbroken plane

The ground plane's job is to be the return conductor of every signal and every power rail on the board, directly beneath each, with no interruption. A whole plane has an impedance of milliohms at DC and a spreading inductance of tens of picohenries between any two points, which is as close to a zero-impedance reference as a board can have. Every trace over it has its return under it. Every capacitor to it has a short loop. Every region of the board is at the same potential to within the noise of the return currents that cross it, and the way to keep that noise away from a sensitive circuit is to keep the noisy currents from crossing under it, which is a matter of placement.

The split-ground myth

Figure 9. The same circuit on a split plane and on one plane. On the split, the ADC bridges the gap and every signal that crosses becomes a loop; on one plane the partition is by placement.

The myth: analog and digital grounds must be separate copper regions, joined at one point, to keep digital noise out of analog. The physics: a signal crossing the split has no return path under it, so its return detours around the end of the split, the loop opens to the length of the detour, and the signal radiates, picks up, and reflects at the crossing. Every trace that crosses the split does this, and something always crosses it: the ADC's own data lines, the supply, the reference. The voltage between the two regions is set by the current forced across the single joining point, which is exactly the common-impedance coupling the split was meant to prevent. Hartley's phrasing: a split creates a slot antenna, and the traces crossing it are the feed.

The alternative that achieves what the split was meant to achieve is partition by placement. Put the analog circuits in one region and the digital circuits in another, on one plane, and let no digital trace enter the analog region. The digital return currents then stay under the digital traces, in the digital region, and the analog region's plane carries only analog returns. The ADC sits on the boundary with its analog pins toward the analog region and its digital pins toward the digital region. This is what the datasheets of every precision ADC vendor now recommend when read carefully; the split-ground drawings in older application notes date from two-layer boards where there was no plane to keep whole.

The one legitimate split is galvanic isolation: two grounds that must be at different potentials, with every crossing made by an isolator, a transformer, or an optocoupler, and nothing else in common. That is not "separating analog and digital"; it is two separate boards that happen to share a laminate.

Where the return current goes when the reference changes

Figure 10. A signal changing layers. The return current has to change planes too. Between two ground planes a nearby via closes the loop; between ground and power the only path is a capacitor.

A signal via moves the signal from one layer to another, and the return current has to move from one plane's surface to another's. Between two ground planes, the return needs a ground via within a few tens of mils of the signal via; without one it spreads out to find the nearest stitching via, and the loop it opens is inductance and a radiating slot. Between a ground plane and a power plane the only path is the nearest capacitor between them, with its mounting inductance in series, and the return detours to it. The rules:

• Route high-speed nets on layers that share a ground reference, or on the two sides of one ground plane.
• Put a ground via next to every signal via on a critical net, closer than a tenth of the wavelength at the knee frequency. For a 1 ns edge that is under about 100 mil; place it as close as the annular rings allow.
• Where a reference change to power is unavoidable, place a 10 to 100 nF capacitor between the two planes adjacent to the via.
• Stitch ground planes together with a via grid at about a tenth of a wavelength at the highest frequency of concern: 100 to 200 mil spacing for a board with 1 ns edges, tighter near high-speed nets and at plane edges.

Two-layer boards and chassis

A two-layer board has no plane worth the name unless one side is left almost entirely as ground and the other carries the signals, with every crossing on the ground side kept short and every trace on the signal side kept over uninterrupted ground. A ground pour full of islands and long slots is worse than a few well-placed return traces, because it looks like a plane and is not. For a two-layer board with a switching converter, the converter's loop must be closed on one layer.

Chassis ground is a separate net that touches the board's ground at the cable ports, in one place per port and as short as possible. The connector shell, the ESD diodes, and the shield of every cable go to chassis; the board's ground bonds to chassis right there, through a direct connection or a high-voltage capacitor if the product requires isolation at low frequency. A bond anywhere else puts the board's noise current through the chassis and out the cable. The noise note covers shield termination.

Terminations and reflections

Figure 11. A 1 V step from a 10 Ω driver into a 50 Ω line with an open end, without and with a series termination. The unterminated line rings for many round trips; the terminated line settles in one flight time.

At every change of impedance a fraction $\rho = (Z_2 - Z_1) / (Z_2 + Z_1)$ of the incident wave reflects. An open end reflects everything with $\rho = +1$, so the voltage there doubles. A low-impedance driver reflects with $\rho$ near $-1$, so the reflection comes back inverted. Between them the wave bounces until the mismatches absorb it. The receiver sees overshoot, undershoot, and a stair-step edge that can cross the threshold more than once.

A series termination is the default for a point-to-point logic signal longer than the critical length. A parallel termination is for multi-drop buses, where the series scheme's half-swing plateau would be seen by the intermediate taps. Fly-by topology with the termination past the last load, as in DDR3 and later, is a parallel termination with the stub lengths kept below the critical length.

Stubs are the hidden reflection. A branch off a line, a via that continues through the board past the layer where the signal leaves it, a test point on a long trace: each is an unterminated line whose reflection arrives at a delay equal to twice the stub length. For a 200 ps edge, a stub over about 50 mil matters. Back-drilling removes the unused part of a through via for this reason on boards above a few gigabits per second; blind or micro vias avoid creating it.

Differential pairs

Figure 12. A differential pair over a plane. Each line's return current is in the plane beneath it, not in the partner line, unless the pair is much closer to each other than to the plane.

A differential pair is two single-ended transmission lines driven with opposite signals. The receiver responds to the difference, which rejects whatever is common to both: ground offset between driver and receiver, common-mode noise picked up along the way, and the reference shift when the pair crosses something. The differential impedance is the impedance seen between the two lines, $Z_{diff} = 2 Z_{odd}$, where the odd-mode impedance is somewhat less than the single-ended $Z_0$ because of the coupling between the lines. For loosely coupled pairs, spacing of two or more heights, $Z_{diff} \approx 2 Z_0$ and the lines can be treated independently.

Where the return current goes is the point most often misunderstood. Each line's return is in the plane directly beneath it, in the opposite direction to the partner's return, and only a fraction is carried by the partner, a fraction that rises as the pair is brought closer together than the height above the plane. A typical 100 Ω pair with spacing equal to the trace width and a 4 mil dielectric has most of its return in the plane. So a pair crossing a plane gap is two single-ended discontinuities. The common-mode rejection of the receiver removes the shared part of the disturbance, but the mode conversion at the gap, the radiation from the two loops, and the impedance discontinuity are not removed. Differential pairs need their reference plane like any other trace; they merely fail more gracefully without it.

The practical rules:

• Keep the pair the same length to within the skew budget, which is a fraction of the bit time: for 5 Gb/s, about 5 to 10 ps, or 1 to 2 mm. Match at the point where the mismatch occurs, not at the far end.
• Keep the spacing constant along the route, since the differential impedance depends on it; open the pair around obstacles only where unavoidable and for as short a distance as possible.
• Route the pair on one layer with the fewest possible vias, and where vias are needed, place them as a pair with ground vias beside them.
• Keep other signals at least three heights away, and other pairs at least three heights away from each other. Tight coupling within a pair does not reduce crosstalk from a neighbor as much as distance does.
• AC-coupling capacitors, ESD diodes, and connector pads are discontinuities; keep them small (0402 or smaller), symmetric between the two lines, and adjacent to each other, and cut the plane under a large pad to restore the impedance if the tool models it.

Crosstalk

Figure 13. Near-end crosstalk against the ratio of spacing to dielectric height for a microstrip. The lever is the ratio, not the spacing alone.

Two traces near each other share fields. The aggressor's edge induces a current in the victim through mutual capacitance and a voltage through mutual inductance; the two add at the near end (the end nearer the aggressor's driver) and subtract at the far end. Near-end crosstalk is a fixed fraction of the aggressor's swing that lasts for twice the coupled length's delay; far-end crosstalk is a pulse that grows with coupled length and with edge rate, and on stripline is nearly zero because the capacitive and inductive parts cancel in a homogeneous dielectric.

The coupling depends on the ratio of spacing to height above the plane, because the height sets how far the fields spread. Bogatin's rule of thumb for a 50 Ω microstrip: near-end crosstalk is about 6 % at a spacing equal to the trace width, under 2 % at twice the width, and about 1 % at three times. The 3W rule that appears in every guideline is this last number. It is a rule for a trace width about twice the height; it is neither necessary on a thin dielectric nor sufficient on a thick one. A board with a 3 mil dielectric can route at a tighter pitch for the same isolation than one with an 8 mil dielectric, and that is the crosstalk argument for thin dielectrics, in addition to the inductance argument.

Guard traces, a grounded trace run between two signals, are of limited value: they work only if stitched to the plane at intervals much shorter than a wavelength, and at that point the same space given to spacing does as well. On a board with a solid adjacent plane, distance and a thin dielectric are the tools. A guard ring around a high-impedance analog node is a different device, for leakage rather than crosstalk, and does work.

Crosstalk is also a timing problem: an aggressor edge arriving during a victim edge shifts the victim's crossing point, which is jitter. For a matched bus the crosstalk budget is part of the timing budget.

The impedance target

Figure 14. Impedance of a power distribution network from the regulator to the die. Each capacitor covers one band; above about 100 MHz only the plane pair and the package are left.

A power rail must hold its voltage within a tolerance while the load draws a current that changes in nanoseconds. The rail looks to the load like an impedance, and the requirement is

$$Z_{target} = \frac{\Delta V_{allowed}}{\Delta I_{max}}$$

A 1 V core rail allowed 50 mV of ripple under a 2.5 A step must present under 20 mΩ from DC to the highest frequency at which the load's current changes, which is the bandwidth of the load's edges, hundreds of megahertz for a digital core. No single component covers that range. The regulator holds the impedance low up to its loop bandwidth, tens of kilohertz to a megahertz. Bulk capacitors, tens to hundreds of microfarads, cover to a few hundred kilohertz before their inductance takes over. Ceramic capacitors of 1 to 10 µF cover to a few megahertz; 100 nF parts to a few tens of megahertz; and above that the only capacitance with low enough inductance is the plane pair itself, then the package and the die.

Each capacitor is a series RLC: below its resonance it is a capacitor, above it an inductor. The inductance is almost entirely the mounting, not the part. Where one capacitor's inductive region meets the next's capacitive region there is a parallel resonance, an anti-resonant peak at which the impedance rises above both. The design of a decoupling network is the management of these peaks: enough capacitors of each value that the peaks stay under the target, and enough resistance (ESR) that they are damped.

Two conclusions follow, both counter to habit. First, many capacitors of the same value in parallel lower the impedance without moving the resonance, and adding a decade-spaced set of values (100 nF, 10 nF, 1 nF) creates anti-resonant peaks between them that may be higher than the impedance would have been with one value; it is a technique that needs simulation, not a default. Second, the capacitor's value matters less than its loop: a 100 nF part with 3 nH of mounting inductance is inductive above 9 MHz, and no choice of value changes that.

Mounting inductance

Figure 15. Three ways to mount the same 0402 capacitor. The loop through the pads, the traces, and the vias to the planes is the inductance, and it varies by nearly an order of magnitude with the layout.

The loop of a decoupling capacitor is the pad, the trace to the via, the via down to the plane, the plane pair, and back up the other via. Its inductance is proportional to the area of that loop. A capacitor with its vias at the ends of long traces has 2 to 3 nH; with the vias at the pad ends, about 1 nH; with vias on both sides of each pad, or via-in-pad, 0.3 to 0.5 nH. The distance to the plane pair adds to it: a plane pair 4 mil below the surface gives a much smaller loop than one 30 mil below. This is a stackup decision, and it is the reason the ground plane goes on layer 2 and the power-ground pair is placed close to the layer that carries the decoupling.

The question of how close the capacitor must be to the IC is answered by the same loop argument. Below a few hundred megahertz the capacitor's own loop inductance dominates, and a capacitor 5 mm away with 0.4 nH is better than one at the pin with 3 nH. Above that, the spreading inductance of the plane between the capacitor and the pin, and the pin's own package inductance, dominate, and only the plane pair and the on-package capacitance help. Put the capacitors close because it costs nothing, but put the vias right because it is what matters.

Plane capacitance and cavity resonance

A power plane and a ground plane on a thin dielectric are a capacitor of $\varepsilon_0 \varepsilon_r A / d$: about 0.9 nF per square inch at 2 mil, 0.45 nF at 4 mil, 0.2 nF at 10 mil. That is small, but it comes with an inductance of picohenries, and so it is the only capacitance that works above a few hundred megahertz. A pair of planes is also a resonant cavity, with its first mode at $c / (2 \ell \sqrt{\varepsilon_r})$: for a 4 inch plane pair on FR-4, about 700 MHz. At the cavity resonances the plane impedance peaks and the edges of the board radiate. Close spacing raises the losses that damp the resonance, and stitching vias with capacitors between the planes at the board edges damp it further. The 20H rule, pulling the power plane back from the edge by twenty times the dielectric thickness, addresses the same radiation; on a thin dielectric with edge stitching it is unnecessary, and on a thick one it is insufficient.

Cables are the antennas

A board is a poor antenna: its longest dimension is a small fraction of a wavelength below a few hundred megahertz. A cable a meter long is a good antenna from 30 MHz up. The current that drives it is the common-mode current, the current that flows out on all the conductors of the cable together and returns through the environment. Its source is the voltage between the point where the cable attaches and the board's reference, which is the ground bounce, the return current across a slot, the power rail noise, whatever the board puts across that path. A few microamps of common-mode current on a one-meter cable is enough to fail a Class B radiated emissions limit at 100 MHz.

Figure 17. Filtering at a cable port. The TVS, the common-mode choke, and the RC sit at the connector, referenced to chassis, before the signal reaches the board ground.

The defenses are at the port. A common-mode choke on the cable's conductors raises the impedance the common-mode current sees without affecting the signal. A filter on each line sets the bandwidth to what the signal needs. The connector shell and the cable shield bond to chassis at the connector, and the board's ground bonds to chassis at the same place, once, so that no board current flows through the chassis path. ESD protection sits at the connector with its return to chassis, so that the ESD current never crosses the board. A ground pour under the connector area, stitched to chassis, is the low-impedance reference for all of it. Every cable port gets this treatment; the one that does not is the one that fails.

Board-level practices

• Stitch every ground plane to every other with a via grid, and stitch the board edges at a spacing under a tenth of the wavelength at the knee frequency.
• Keep clocks and switch nodes away from the board edges and away from connectors.
• Do not route any signal over a plane gap or off the edge of a plane, including under connectors, near mounting holes, and around cutouts.
• Terminate every clock and every fast edge. An unterminated edge rings at the resonance of the trace, and that ringing has a spectrum that peaks exactly where the emissions test looks.
• Slow the edges where the design allows. A series resistor at every non-critical driver, 22 to 33 Ω, costs nothing and removes the top decade of the spectrum.
• Spread-spectrum clocking lowers the peak of each harmonic by spreading it; it helps the measurement more than it helps the neighbor.
• Shielding cans work when the can is bonded to the plane around its entire perimeter at a spacing under a tenth of a wavelength; a can with a few tabs is a resonator.
• Mounting holes that bond the board to a metal chassis at several points give the board a low-impedance reference to the chassis and lower the common-mode drive to every cable. Use them.