Vout = Vin × (R2 / (R1 + R2)) - leave one field empty to solve
Nearest standard resistor value to a calculated target - works for any E-series part
Read the bands left to right with the tolerance band on the right. 3 bands: two digits and a multiplier. 4 bands add tolerance. 5 bands use three digits
Best standard resistor pairs for a target Vout = Vin × R2 / (R1 + R2)
R = (Vs - Vf) / If, rounded up to E24
read more: Useful Discrete Circuits: current sources
Time for a capacitor charging toward Vs to cross Vth: t = -RC × ln(1 - Vth/Vs)
read more: Op-Amp Cheat Sheet: standard circuits, Capacitor Selection: selection by circuit function
Copper wire resistance, one-way voltage drop, and rule-of-thumb ampacity (~4 A/mm² bundled, ~10 A/mm² in free air)
read more: Connectors and Cables: wire
Copper resistance corrected for temperature: R = R20 × (1 + 0.00393 × (T - 20)). Round trip doubles the conductor length. Supply voltage is optional and gives the percentage drop and the voltage at the load
read more: Connectors and Cables: wire, Noise in Circuits: grounding
Solid copper at 20 °C. Ampacity columns are the same rules of thumb as the wire gauge calc (4 A/mm² bundled, 10 A/mm² single conductor in free air), not a code rating; use the applicable standard for mains and building wiring
| AWG | dia (mm) | area (mm²) | Ω / km | A bundled | A free air |
|---|---|---|---|---|---|
| 0 | 8.251 | 53.475 | 0.32 | 213.90 | 534.75 |
| 1 | 7.348 | 42.408 | 0.41 | 169.63 | 424.08 |
| 2 | 6.544 | 33.631 | 0.51 | 134.52 | 336.31 |
| 3 | 5.827 | 26.670 | 0.65 | 106.68 | 266.70 |
| 4 | 5.189 | 21.151 | 0.82 | 84.60 | 211.51 |
| 5 | 4.621 | 16.773 | 1.03 | 67.09 | 167.73 |
| 6 | 4.115 | 13.302 | 1.30 | 53.21 | 133.02 |
| 7 | 3.665 | 10.549 | 1.63 | 42.20 | 105.49 |
| 8 | 3.264 | 8.366 | 2.06 | 33.46 | 83.66 |
| 9 | 2.906 | 6.634 | 2.60 | 26.54 | 66.34 |
| 10 | 2.588 | 5.261 | 3.28 | 21.04 | 52.61 |
| 11 | 2.305 | 4.172 | 4.13 | 16.69 | 41.72 |
| 12 | 2.053 | 3.309 | 5.21 | 13.24 | 33.09 |
| 13 | 1.828 | 2.624 | 6.57 | 10.50 | 26.24 |
| 14 | 1.628 | 2.081 | 8.28 | 8.32 | 20.81 |
| 15 | 1.450 | 1.650 | 10.45 | 6.60 | 16.50 |
| 16 | 1.291 | 1.309 | 13.17 | 5.23 | 13.09 |
| 17 | 1.150 | 1.038 | 16.61 | 4.15 | 10.38 |
| 18 | 1.024 | 0.823 | 20.95 | 3.29 | 8.23 |
| 19 | 0.912 | 0.653 | 26.41 | 2.61 | 6.53 |
| 20 | 0.812 | 0.518 | 33.31 | 2.07 | 5.18 |
| 21 | 0.723 | 0.410 | 42.00 | 1.64 | 4.10 |
| 22 | 0.644 | 0.326 | 52.96 | 1.30 | 3.26 |
| 23 | 0.573 | 0.258 | 66.78 | 1.03 | 2.58 |
| 24 | 0.511 | 0.205 | 84.21 | 0.82 | 2.05 |
| 25 | 0.455 | 0.162 | 106 | 0.65 | 1.62 |
| 26 | 0.405 | 0.129 | 134 | 0.52 | 1.29 |
| 27 | 0.361 | 0.102 | 169 | 0.41 | 1.02 |
| 28 | 0.321 | 0.081 | 213 | 0.32 | 0.81 |
| 29 | 0.286 | 0.064 | 268 | 0.26 | 0.64 |
| 30 | 0.255 | 0.051 | 339 | 0.20 | 0.51 |
| 31 | 0.227 | 0.040 | 427 | 0.16 | 0.40 |
| 32 | 0.202 | 0.032 | 538 | 0.13 | 0.32 |
| 33 | 0.180 | 0.025 | 679 | 0.10 | 0.25 |
| 34 | 0.160 | 0.020 | 856 | 0.08 | 0.20 |
| 35 | 0.143 | 0.016 | 1079 | 0.06 | 0.16 |
| 36 | 0.127 | 0.013 | 1361 | 0.05 | 0.13 |
| 37 | 0.113 | 0.010 | 1716 | 0.04 | 0.10 |
| 38 | 0.101 | 0.008 | 2164 | 0.03 | 0.08 |
| 39 | 0.090 | 0.006 | 2729 | 0.03 | 0.06 |
| 40 | 0.080 | 0.005 | 3441 | 0.02 | 0.05 |
read more: Connectors and Cables: wire
°F = °C × 9/5 + 32, K = °C + 273.15
Rmin from VOL sink current (0.4 V spec), Rmax from rise time: tr = 0.8473 × R × Cb. Standard mode 1000 ns, fast mode 300 ns
C1 = C2 = 2 × (CL - Cstray). CL from the crystal datasheet; stray is typically 3-5 pF of pin + trace capacitance
read more: Capacitor Selection: selection by circuit function, PCB Layout: placement
LSB = Vref / 2^N, ideal SNR = 6.02N + 1.76 dB (full-scale sine)
read more: ADC Front-End: resolution, noise, and ENOB
ENOB = (SINAD - 1.76) / 6.02 for a full-scale sine. SINAD includes noise and distortion; use SNR alone for the noise-only figure. Quantization noise of an ideal N-bit converter is 1 LSB / √12 RMS
read more: ADC Front-End: resolution, noise, and ENOB
Astable: f = 1.44 / ((R1 + 2R2) × C), high = 0.693 (R1 + R2) C, low = 0.693 R2 C, so duty is always above 50 % (add a diode across R2 for less). Monostable: t = 1.1 × R × C
read more: Capacitor Selection: selection by circuit function
R = R25 × exp(β × (1/T - 1/298.15)) - fill T or R, leave the other empty to solve
read more: Useful Discrete Circuits: sensors from ordinary parts
P = I² × Rds(on), Tj = Ta + (P × θja)
read more: MOSFET Crash Course: conduction and switching losses, Thermal Design: the thermal resistance model
Psw = Qg × Vgs × fsw, Pcond = I² × Rds(on)
read more: MOSFET Crash Course: conduction and switching losses, gate drive and the Miller plateau
GBP = Gain × Bandwidth - leave one field empty to solve
read more: Op-Amp Cheat Sheet: datasheet parameters
Non-inverting: G = 1 + Rf/Rg. Inverting: G = -Rf/Rg. Noise gain 1 + Rf/Rg sets the closed-loop bandwidth GBP / noise gain for either topology. Rails and GBP are optional
read more: Op-Amp Cheat Sheet: standard circuits, common design errors
Best standard Rf / Rg pairs for a target gain. Keep Rg in the 1 k to 10 k range for most op-amps: lower loads the output, higher adds noise and offset from bias current
read more: Op-Amp Cheat Sheet: standard circuits
fc = 1 / (2πRC) - leave one field empty to solve
read more: ADC Front-End: anti-alias filter design, Capacitor Selection: selection by circuit function
fc = 1 / (2πRC), same corner as the low pass with C and R swapped. Also the AC-coupling corner for a series cap into a load R. Leave one field empty to solve
read more: Op-Amp Cheat Sheet: standard circuits
XL = 2πfL, XC = 1 / (2πfC). An L and C together resonate at f0 = 1 / (2π√LC) with characteristic impedance Z0 = √(L/C), which sets how much the pair rings. Enter any two or all three
read more: Inductors and Magnetics: self-resonance and high frequency, Capacitor Selection: what a capacitor actually is, Ferrite Beads: resonance with the capacitance around it, PCB Layout: power integrity
Unity-gain, equal-R design: C1 = 4Q² × C2, R1 = R2 = 1/(4πQ × fc × C2). fc is the pole (natural) frequency; the -3 dB point is reported below
Q and damping. A second-order low pass is set by its natural frequency fc and its quality factor Q. The damping ratio is ζ = 1 / (2Q). Q below 0.5 gives two real poles and a sluggish, overdamped response; Q = 0.5 is critically damped; Q above 0.5 gives a complex pole pair and a step response that overshoots. Q above 0.707 also peaks the magnitude response near fc. Peaking in dB is 20 log(Q / √(1 - 1/(4Q²))). Step overshoot is exp(-πζ / √(1 - ζ²)). The -3 dB frequency equals fc only for Butterworth; for lower Q it sits below fc, for higher Q above.
Critically damped (Q = 0.5, ζ = 1). No overshoot and the fastest rise that stays monotonic. -3 dB at 0.64 fc. Same alignment as a second-order Linkwitz-Riley crossover and as two identical buffered RC sections. Use for anti-alias or reconstruction stages where any overshoot on a step is unacceptable, at the cost of the slowest rolloff near the corner.
Bessel (Q = 0.577, ζ = 0.866). Maximally flat group delay: all frequencies in the passband are delayed by the same amount, so pulse and square wave shapes pass through with the least distortion. Step overshoot about 0.4 %, -3 dB at 0.79 fc. Gentle magnitude rolloff. Use for data, video, and audio paths where waveform fidelity matters more than a sharp corner.
Butterworth (Q = 0.707, ζ = 0.707). Maximally flat magnitude: no ripple in the passband and the sharpest corner that is still monotonic in frequency. -3 dB exactly at fc. Step overshoot about 4.3 % with a single visible ring. The default choice when the spec is written in terms of a corner frequency and passband flatness.
Chebyshev (Q above 0.707). Trades passband ripple for a steeper transition. The dB label is the allowed ripple; a 0.5 dB design has Q = 0.864, 1 dB has Q = 0.957, 2 dB has Q = 1.129, 3 dB has Q = 1.305. For a single second-order section the ripple appears as a peak of that height near fc. Step response overshoots 11 % (0.5 dB) to 27 % (3 dB) and rings for several cycles. -3 dB sits above fc, at 1.18 fc for 0.5 dB up to 1.39 fc for 3 dB. Use when rejection just past the corner matters and the signal is narrowband or steady state.
Custom Q. Enter any value. Typing in the Q field switches the dropdown to custom. Values above about 5 are impractical in a unity-gain Sallen-Key: C1 = 4Q² × C2 forces a large capacitor ratio, and the response becomes very sensitive to component tolerance and to the opamp's output impedance at high frequency.
Practical limits. Use 1 % resistors and 5 % or better C0G/NP0 capacitors; X7R shifts fc and Q with voltage and temperature. Keep the opamp gain-bandwidth at least 100 × Q × fc so the amplifier does not add its own pole inside the filter. Cascade two sections with different Q values (for example 0.541 and 1.307 for a fourth-order Butterworth) for a higher-order response.
read more: ADC Front-End: anti-alias filter design, Op-Amp Cheat Sheet: standard circuits
Sine-wave conversions at a given impedance: P = Vrms²/Z, Vpp = 2√2 × Vrms, dBµV = 20 log(Vrms / 1 µV) (so dBµV = dBm + 107 at 50 Ω). Enter one value, leave the rest empty
Two signals at different dB levels. Given a level and value for A, the level of B gives its value (or the reverse). Ratio B/A = 10^(ΔdB / 20) for voltage, 10^(ΔdB / 10) for power. Leave one field empty to solve
read more: Oscilloscope Probing: bandwidth, rise time, and sample rate
Resistor noise density en = √(4 k T R). Any density (resistor, op-amp, reference) times √bandwidth gives the RMS; ×6.6 is the usual peak-to-peak estimate (99.9 % of Gaussian samples). Leave R empty to use an entered density instead
read more: Noise in Circuits: intrinsic noise, Op-Amp Cheat Sheet: part selection
Estimates runtime based on capacity, sleep power, and TX events
Average current = Σ(I × t) / Σt over one cycle, runtime = usable capacity / Iavg. Usable % covers cutoff voltage, temperature, and aging; 80 % is a fair starting point for Li-ion, less for alkaline at high drain. Leave a state empty to skip it
C-rate = I / capacity (1C empties or fills in one hour). Constant-current time = capacity / I. Li-ion CC/CV adds a constant-voltage tail, typically 30 % more; the estimate here uses 1.3×. Stay within the cell's rated charge C-rate
L = (Vout × (Vin - Vout)) / (Vin × fsw × ΔI)
read more: Inductors and Magnetics: the two current ratings, SMPS Crash Course: topologies, continuous and discontinuous conduction
D = 1 - Vin/Vout, L = (Vin × D) / (fsw × ΔIL). Note the inductor carries the input current: IL = Iout / (1 - D)
read more: Inductors and Magnetics: the two current ratings, SMPS Crash Course: topologies, continuous and discontinuous conduction
ΔVout = ΔIL × ESR + ΔIL / (8 × fsw × C). ΔIL from the inductor sizing calc above
read more: SMPS Crash Course: traps in controller ICs and reference designs, Capacitor Selection: ceramic capacitors
The output cap carries the whole load while the switch is on: ΔVc = Iout × D / (fsw × C). The diode current steps to the inductor peak, so ESR adds Ipk × ESR, usually the larger term with electrolytics
read more: SMPS Crash Course: traps in controller ICs and reference designs, Capacitor Selection: aluminum electrolytic capacitors
Error amplifier with R2, C1 in series and C2 in parallel, fed from the upper divider resistor R1. Mid-band gain = R2 / R1, zero at 1 / (2π R2 C1), pole at 1 / (2π R2 (C1 ∥ C2)). Enter the crossover to see the phase boost
read more: SMPS Crash Course: compensation networks, control theory for the loop
Reflected voltage Vr = N (Vout + Vf), Dmax = Vr / (Vin,min + Vr). Switch sees Vin,max + Vr plus the leakage spike; diode sees Vout + Vin,max / N. Lp is the CCM/DCM boundary value at Vin,min; go larger for CCM, smaller for DCM
read more: SMPS Crash Course: isolated converters, Inductors and Magnetics: coupled inductors and transformers
Leakage energy ½ L Ipk² each cycle, scaled by Vclamp / (Vclamp - Vr) because the clamp also draws from the reflected voltage. R = Vclamp² / P. C sized for the allowed ripple: C = Vclamp / (ΔV × R × fsw). Aim for Vclamp of 1.5 to 2 × Vr
read more: SMPS Crash Course: isolated converters, Inductors and Magnetics: coupled inductors and transformers
P = (Vin - Vout) × I, Tj = Ta + P × θja - the 'do I need a heatsink' check
read more: Thermal Design: the board as a heatsink, SMPS Crash Course: the energy picture, Capacitor Selection: selection by circuit function
Tj = Ta + P × (θjc + θcs + θsa). Leave θsa empty and enter a Tj limit to get the heatsink you need. Use θjc from the datasheet, not θja, when a heatsink or copper pour carries the heat
read more: Thermal Design: the thermal resistance model, external heatsinks
P = I²rms × ESR, estimates temperature rise
read more: Capacitor Selection: aluminum electrolytic capacitors, derating summary
Measure the switch-node ring frequency (f1), add a test cap and measure again (f2). R = √(Lpar/Cpar), Csnub ≈ 3 × Cpar
read more: PCB Layout: high di/dt and high dV/dt circuits, Oscilloscope Probing: switch node and gate drive
Minimum width for a current and allowed temperature rise: I = k × ΔT^0.44 × A^0.725. Resistance at 20 °C for the computed width
read more: PCB Layout: routing critical nets, Thermal Design: the board as a heatsink
Calculates characteristic impedance for microstrip or stripline
read more: PCB Stackup: impedance constraints, PCB Layout: the physics that drives everything
Solves the microstrip / stripline formulas from the trace impedance calc for width. Confirm with the fab's field solver before release; εr and the pressed dielectric thickness are theirs
read more: PCB Stackup: impedance constraints, PCB Layout: routing critical nets
Grounded coplanar waveguide: trace of width w with gap s to coplanar ground on each side, over a plane at height h. Conformal-mapping solution (Wadell). Stitch the side grounds to the plane within λ/10 of the highest frequency
read more: PCB Stackup: impedance constraints
Edge-coupled pair (IPC-2141 approximation) - for USB, RS-485, Ethernet etc.
read more: PCB Stackup: impedance constraints, PCB Layout: routing critical nets
Barrel treated as an internal IPC-2221 conductor. L ≈ 0.2 × h × (ln(4h/d) + 1) nH
read more: Thermal Design: the board as a heatsink, PCB Layout: grounding and the return path, PCB Stackup: drill aspect ratio
Partial self-inductance of a straight trace far from its return path: L ≈ 0.2 l (ln(2l / (w + t)) + 0.5 + 0.2235 (w + t) / l) nH with dimensions in mm. Over a solid plane the loop inductance is much lower; this is the number for a trace with no nearby return, such as a decoupling cap lead
read more: PCB Layout: power integrity
Parallel-plate C = ε0 εr A / d between two copper planes. Thin power-ground spacing (0.1 mm or less) gives useful high-frequency decoupling with near-zero inductance; at typical 0.2 to 1 mm spacing it is small
read more: PCB Layout: power integrity, PCB Stackup: impedance constraints
BW = 0.35 / tr (10 to 90 %). Knee frequency 0.5 / tr is where edge energy runs out. A trace needs transmission-line treatment once its delay exceeds about tr / 6; tr / 2 is the round-trip limit where reflections merge into the edge
read more: PCB Layout: the physics that drives everything, Oscilloscope Probing: bandwidth, rise time, and sample rate
Γ = (Z - Z0) / (Z + Z0) at each end. Return loss = -20 log |Γ|, VSWR = (1 + |Γ|) / (1 - |Γ|). With a source impedance the launch step is Z0 / (Zs + Z0) of the driver swing and the first arrival at the load is launch × (1 + ΓL)
read more: PCB Layout: routing critical nets, Oscilloscope Probing: coupling, termination, and the input path
Safety spacing per IEC 60664-1 (clearance from the rated impulse voltage, creepage from working voltage, pollution degree and material group) alongside the IPC-2221B functional spacing table. Tables are as published; the standard and your product standard govern.
Clearance (shortest path through air) is dimensioned against transients. The rated impulse voltage comes from the supply's nominal line-to-neutral voltage and the overvoltage category (Table F.1), or from the peak working voltage plus 1200 V for circuits that see no mains transients. Table F.2 converts it to a distance for the pollution degree. The distance is also checked against the steady-state peak (Table F.7a) and the larger governs. Above 2000 m the distance is multiplied by the Table A.2 factor. Reinforced insulation uses the next impulse value in the preferred series and 160 % of the steady-state peak.
Creepage (shortest path along the insulating surface) is dimensioned against tracking under long-term working voltage. Table F.4 gives it from the RMS or DC working voltage, the pollution degree and the material group; the printed wiring columns apply to conductors on a printed board under pollution degrees 1 and 2 up to 1000 V. Reinforced insulation doubles the basic value. Creepage may never be less than the clearance. The table is entered at the next higher voltage row; the standard permits linear interpolation between rows.
IPC-2221B Table 6-1 is a design guideline for proper functional operation, not a safety standard. It is entered with peak or DC voltage, gives spacing for internal and external layers with and without coating, and adds a per-volt increment above 500 V. IPC-9592B (computer and telecom power conversion) is slightly more conservative.
Pollution degree. 1: no pollution or dry non-conductive pollution only (sealed, potted, or conformally coated to exclude condensation). 2: non-conductive pollution with occasional condensation (offices, homes, equipment enclosures). 3: conductive pollution, or dry pollution that becomes conductive through expected condensation (industrial, unheated rooms). 4: persistent conductivity from dust, rain or snow; outside the scope of these tables.
Overvoltage category. I: circuits with transient limiting (transformer-fed 24 V controls). II: equipment plugged into the fixed installation (appliances, portable tools). III: fixed installation and distribution (panels, hardwired industrial machinery). IV: origin of the installation (meters, primary overcurrent protection).
Material group by comparative tracking index: I ≥ 600, II 400 to 599, IIIa 175 to 399, IIIb 100 to 174 or unspecified. Most FR-4 is IIIa; isolator IC packages are often group I, which is why the PCB rather than the part sets the creepage.
Product standards refine these values: IEC 62368-1 (audio, video, IT and communications) Tables 10 and 17, IEC 61800-5-1 (drives) Tables 9 and 10, IEC 62109-1 (solar) Tables 13 and 14. Their clearances for a given impulse are somewhat larger (for example 1.8 mm rather than 1.5 mm at 2.5 kV in IEC 62368-1). Conformal coating per IEC 60664-3 can reduce the pollution degree under the coating. Frequencies above 30 kHz are covered by IEC 60664-4.
read more: PCB Stackup: voltage and dielectric spacing, Connectors and Cables: voltage rating, ESD, Surge, and Protection: placement and layout